Perry E. Metzger writes:
> Michael Thomas <[EMAIL PROTECTED]> writes:
> > Perry E. Metzger writes:
> > > I'm looking for statements from several router vendors that look much
> > > like this:
> >
> > I don't speak for Cisco. I speak for myself.
> >
> > Sorry.
>
> Well, speaking for yourself, can you describe your simulations of
> hardware performance with and without the flow label?
I'm not especially interested in this game
because some hardware geek somewhere is
bound to throw enough transistors at the
problem and claim that it doable. Big deal.
It's an empty claim because it doesn't say
what was given up in the process. I have
witnessed firsthand hardware engineers on
high end platforms react somewhere between
disbelief and outright hostility at the
prospect of chasing down header chains at
line rate. CAM's -- as I've mention three
times now -- are especially sensitive to
bone headed standards potato blunders of
this kind; I forget, but the transistor
count is O(n^2) or maybe worse with the
number of bits needed to form the key. IP6
is already at a big disadvantage given the
need to key off of ~256 bits vs. 64 bits
just for addresses. And lest you think
that I'm just concerned about CAM based forwarding
planes, think again; they all need to view
enough of the header to classify, and that
always impacts silicon as it gets bigger.
Thus you get these choices: pay more than you
should have, get worse performance, or delete
other features you might have liked to go
faster on a finite transistor budget.
Oh, and you might ask your hardware vendors
who claim to do this whether they can deal
with flow classification of mobile IP with
route optimization at line rate. And since
MIPv6 route optimization is about as stable as
jello, will they have the resilience to change
their flow classier if it changes too?
Mike
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