--- src/drivers/net/tg3/tg3_hw.c	2012-08-20 18:22:15.764715313 -0400
+++ src/drivers/net/tg3/tg3_hw-new.c	2012-10-08 20:28:12.868033625 -0400
@@ -316,14 +316,14 @@
 		}
 
 		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
-			tg3_flag_set(tp, ENABLE_ASF);
-			if (tg3_flag(tp, 5750_PLUS))
-				tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
-		}
-
-		if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
-		    tg3_flag(tp, 5750_PLUS))
-			tg3_flag_set(tp, ENABLE_APE);
+                        tg3_flag_set(tp, ENABLE_ASF);
+                        if (tg3_flag(tp, 5750_PLUS))
+                                tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
+                }
+
+                if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
+                     tg3_flag(tp, ENABLE_ASF))
+                        tg3_flag_set(tp, ENABLE_APE);
 
 		if (cfg2 & (1 << 17))
 			tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
@@ -466,6 +466,7 @@
 		tg3_flag_set(tp, 5717_PLUS);
 
 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766 ||
 	    tg3_flag(tp, 5717_PLUS))
 		tg3_flag_set(tp, 57765_PLUS);
 
@@ -1465,6 +1466,12 @@
 		tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
 	}
 
+	if (tg3_flag(tp, CPMU_PRESENT)) {
+                tw32(TG3_CPMU_D0_CLCK_POLICY, 0);
+                val = tr32(TG3_CPMU_CLCK_ORIDE_EN);
+                tw32(TG3_CPMU_CLCK_ORIDE_EN, val | CPMU_CLCK_ORIDE_MAC_CLCK_ORIDE_EN);
+        }
+        
 	return 0;
 }