On 03/29/2018 11:20 AM, Mark Rutland wrote: > Hi, > > On Wed, Mar 28, 2018 at 10:19:50PM +0200, Heinrich Schuchardt wrote: >> Without the flag a "data abort" occured when compiling with gcc 6.3 for >> armhf and running on an Allwinner A20 SOC in function efi_devpath_end(). > > I think this may be a bug in the UEFI implementation (which I guess is > U-Boot?). In the 2.7 UEFI spec, section 2.3.5 states that for AArch32: > > Unaligned access should be enabled if supported; Alignment faults are > enabled otherwise. > > All ARMv6 and ARMv7 CPUs (including the COrtex-A7s in the A20 SoC) > support unaligned accesses to normal memory, as would be the case for > memory accessed by efi_devpath_end(). > > Unless GCC is generating misaligned LDM/STM instructions, I believe this > is a FW bug that would be worth reporting, regardless of whether this > patch is taken on the IPXE side.
Hello Mark, thank you for the information. I have unset bit 1 (alignment bit) of the system control register in U-Boot. Now iPXE snp.efi works on the Allwinner A20 without using -mno-unaligned-access. I will try upstreaming a patch for this: diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 7e2695761e..1771741119 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -150,7 +150,6 @@ ENTRY(cpu_init_cp15) mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) - orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB #ifdef CONFIG_SYS_ICACHE_OFF bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache Best regards Heinrich _______________________________________________ ipxe-devel mailing list ipxe-devel@lists.ipxe.org https://lists.ipxe.org/mailman/listinfo.cgi/ipxe-devel