On Tue, 25 Sep 2012, David Blubaugh wrote:
I was wondering if any one was ever validate VHDL or Verilog with
Isabelle HOL ?? Has any one developed a means to check for correctness
of a preexisting VHDL file ??
If you ask on the isabelle-users mailing list, you get a much larger
audience.
isabelle-dev is for the development process of Isabelle itself, not
development of theories and tools with Isabelle.
Makarius_______________________________________________
isabelle-dev mailing list
[email protected]
https://mailmanbroy.informatik.tu-muenchen.de/mailman/listinfo/isabelle-dev
