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https://issues.apache.org/jira/browse/HBASE-19357?page=com.atlassian.jira.plugin.system.issuetabpanels:comment-tabpanel&focusedCommentId=16280841#comment-16280841
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stack edited comment on HBASE-19357 at 12/6/17 9:26 PM:
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Commit this and open new issue for meta blocks I'd say. I'd like to see some 
numbers on size of prob first. It is years since we did heap vs BC compare. 
About time for a redo. A new issue with compare between onheap, offheap, and 
file-backed is overdue.

in hbase2, master carries no regions.


was (Author: stack):
Commit this and open new issue for meta blocks I'd say. I'd like to see some 
numbers on size of prob first.

in hbase2, master carries no regions.

> Bucket cache no longer L2 for LRU cache
> ---------------------------------------
>
>                 Key: HBASE-19357
>                 URL: https://issues.apache.org/jira/browse/HBASE-19357
>             Project: HBase
>          Issue Type: Sub-task
>            Reporter: Anoop Sam John
>            Assignee: Anoop Sam John
>             Fix For: 2.0.0-beta-1
>
>         Attachments: HBASE-19357.patch, HBASE-19357.patch, 
> HBASE-19357_V2.patch, HBASE-19357_V3.patch, HBASE-19357_V3.patch
>
>
> When Bucket cache is used, by default we dont configure it as an L2 cache 
> alone. The default setting is combined mode ON where the data blocks to 
> Bucket cache and index/bloom blocks go to LRU cache. But there is a way to 
> turn this off and make LRU as L1 and Bucket cache as a victim handler for L1. 
> It will be just L2.   
> After the off heap read path optimization Bucket cache is no longer slower 
> compared to L1. We have test results on data sizes from 12 GB.  The Alibaba 
> use case was also with 12 GB and they have observed a ~30% QPS improve over 
> the LRU cache.
> This issue is to remove the option for combined mode = false. So when Bucket 
> cache is in use, data blocks will go to it only and LRU will get only index 
> /meta/bloom blocks.   Bucket cache will no longer be configured as a victim 
> handler for LRU.
> Note : WHen external cache is in use, there only the L1 L2 thing comes. LRU 
> will be L1 and external cache act as its L2. That make full sense.



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