Hello, Hope you are doing well!
Currently we are looking for *Verification Engineer - San Diego, CA* *JOB DETAIL* Job Title Verification Engineer Job id 45650 Job Location San Diego, CA Job Duration 12 month(s)+ (Contract) *Job Description: * · Fluent in System *Verilog HVL and hands-on on Verilog HDL.* · Hands on experience in developing source code with reasonable complexity. · Hands on experience in deriving the features for the block / cluster under verification starting from scratch or from the legacy. · Hands on experience in developing feature list, test plan and test bench strategies for the DUTs. · Working knowledge of EDA tools*(NCSim, VCS, QuestaSim, IUS)* · Verification of complex RTL design IP / complex FPGA design / SoC at module level and system level. · Experience in methodology Test Harness, *UVM OR OVM OR VMM [Min 2 Years of experience in any of the methodology]* · Working knowledge of Unix, shell or Perl scripting. ------------------------------ *Please send resume at **[email protected]* <[email protected]> Hangouts <https://hangouts.google.com/> : [email protected] -- You received this message because you are subscribed to the Google Groups "it req" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at https://groups.google.com/group/it-req. For more options, visit https://groups.google.com/d/optout.
