--- ivtv/driver/cx25840-registers.h	(revision 233)
+++ ivtv/driver/cx25840-registers.h	(working copy)
@@ -338,9 +338,11 @@
 	SRC1_Phase_Increment_Low,
 	SRC1_Phase_Increment_Mid,
 	SRC1_Phase_Increment_High,
+	SRC1_FIFO_Read_Threshold,
 	SRC2_Phase_Increment_Low,
 	SRC2_Phase_Increment_Mid,
 	SRC2_Phase_Increment_High,
+	SRC2_FIFO_Read_Threshold,
 	SRC3_Phase_Increment_Low,
 	SRC3_Phase_Increment_Mid,
 	SRC3_Phase_Increment_High,
@@ -1004,7 +1006,9 @@
 #define CX25840_SET_Sample_Rate_Converter_Status1_REG(value) CX25840__SEQUENCE_14BIT(Sample_Rate_Converter_Status1_REG,  value)
 #define CX25840_SET_Sample_Rate_Converter_Status2_REG(value) CX25840__SEQUENCE_14BIT(Sample_Rate_Converter_Status2_REG,  value)
 #define CX25840_SET_SRC1_PHASE_INC(value) CX25840__SEQUENCE_22BIT(SRC1_PHASE_INC,  value)
+#define CX25840_SET_SRC1_FIFO_RD_TH(value) CX25840__SEQUENCE_6BIT(SRC1_FIFO_RD_TH,  value)
 #define CX25840_SET_SRC2_PHASE_INC(value) CX25840__SEQUENCE_22BIT(SRC2_PHASE_INC,  value)
+#define CX25840_SET_SRC2_FIFO_RD_TH(value) CX25840__SEQUENCE_6BIT(SRC2_FIFO_RD_TH,  value)
 #define CX25840_SET_SRC3_PHASE_INC(value) CX25840__SEQUENCE_22BIT(SRC3_PHASE_INC,  value)
 #define CX25840_SET_SRC3_FIFO_RD_TH(value) CX25840__SEQUENCE_6BIT(SRC3_FIFO_RD_TH,  value)
 #define CX25840_SET_SRC4_PHASE_INC(value) CX25840__SEQUENCE_22BIT(SRC4_PHASE_INC,  value)
--- ivtv/driver/cx25840-registers.c	(revision 233)
+++ ivtv/driver/cx25840-registers.c	(working copy)
@@ -307,9 +307,11 @@
 	DEFINE_REGISTER_INFO_ENTRY(0x08f8, RW),
 	DEFINE_REGISTER_INFO_ENTRY(0x08f9, RW),
 	DEFINE_REGISTER_INFO_ENTRY(0x08fa, RW),
+	DEFINE_REGISTER_INFO_ENTRY(0x08fb, RW),
 	DEFINE_REGISTER_INFO_ENTRY(0x08fc, RW),
 	DEFINE_REGISTER_INFO_ENTRY(0x08fd, RW),
 	DEFINE_REGISTER_INFO_ENTRY(0x08fe, RW),
+	DEFINE_REGISTER_INFO_ENTRY(0x08ff, RW),
 	DEFINE_REGISTER_INFO_ENTRY(0x0900, RW),
 	DEFINE_REGISTER_INFO_ENTRY(0x0901, RW),
 	DEFINE_REGISTER_INFO_ENTRY(0x0902, RW),
@@ -673,9 +675,11 @@
 	"SRC1_Phase_Increment_Low",
 	"SRC1_Phase_Increment_Mid",
 	"SRC1_Phase_Increment_High",
+	"SRC1_FIFO_Read_Threshold",
 	"SRC2_Phase_Increment_Low",
 	"SRC2_Phase_Increment_Mid",
 	"SRC2_Phase_Increment_High",
+	"SRC2_FIFO_Read_Threshold",
 	"SRC3_Phase_Increment_Low",
 	"SRC3_Phase_Increment_Mid",
 	"SRC3_Phase_Increment_High",
@@ -3081,14 +3085,9 @@
 	{0, 0}
 };
 
-#define DEFINE_SETTING_ENTRY(name, rname, sbit, bitl, type, default, vptr, des) { (((rname)&0x1ff)<<0)|(((sbit)&0x7)<<9)|(((bitl)&0x1f)<<12)|(((type)&0xf)<<17),default, name, vptr, des }
+#define DEFINE_SETTING_ENTRY(name, rname, sbit, bitl, type, default, vptr, des) { (((rname)&0x1ff)<<0)|(((sbit)&0x7)<<9)|(((bitl)&0x1f)<<12)|(((type)&0xf)<<17), default, name, vptr, des }
 #else
-
-value_map NULL__value_map[] = {
-	{0, 0}
-};
-
-#define DEFINE_SETTING_ENTRY(name, rname, sbit, bitl, type, default, vptr, des) { (((rname)&0x1ff)<<0)|(((sbit)&0x7)<<9)|(((bitl)&0x1f)<<12)|(((type)&0xf)<<17),default, "", NULL__value_map, "" }
+#define DEFINE_SETTING_ENTRY(name, rname, sbit, bitl, type, default, vptr, des) { (((rname)&0x1ff)<<0)|(((sbit)&0x7)<<9)|(((bitl)&0x1f)<<12)|(((type)&0xf)<<17), default, "", 0, "" }
 #endif
 
 cx25840_setting_entry cx25840_settings[] = {
@@ -4709,9 +4708,15 @@
 	DEFINE_SETTING_ENTRY("SRC1_PHASE_INC", SRC1_Phase_Increment_Low, 0, 18,
 			     RW, 0x01867c, 0,
 			     "Low byte of SRC 1 phase increment value. Calculated by"),
+	DEFINE_SETTING_ENTRY("SRC1_FIFO_RD_TH", SRC1_FIFO_Read_Threshold, 0, 4,
+			     RW, 0x0008, 0,
+			     "SRC 1 FIFO threshold for Read Enable. Apply to both left"),
 	DEFINE_SETTING_ENTRY("SRC2_PHASE_INC", SRC2_Phase_Increment_Low, 0, 18,
 			     RW, 0x01867c, 0,
 			     "Low byte of SRC 2 phase increment value. Calculated by"),
+	DEFINE_SETTING_ENTRY("SRC2_FIFO_RD_TH", SRC2_FIFO_Read_Threshold, 0, 4,
+			     RW, 0x0008, 0,
+			     "SRC 2 FIFO threshold for Read Enable. Apply to both left"),
 	DEFINE_SETTING_ENTRY("SRC3_PHASE_INC", SRC3_Phase_Increment_Low, 0, 18,
 			     RW, 0x014faa, 0,
 			     "Low byte of SRC 3 phase increment value. Calculated by"),