On 16-Jun-16 19:06, Jan Kiszka wrote: > This is my stack of patches that piled up while walking through the > interrupt injection logic of arm (and soon also arm64). Besides a lot of > more or less minor cleanups, it primarily reworks the software queue for > pending interrupts into a ring and fixes setup, handling and protection > of the maintenance interrupt. > > One open issue, though still a minor one: We should probably bring all > distributor registers related to hypervisor SGIs and the maintenance > interrupt into defined state during handover from Linux. > > The whole thing is lightly tested so far, only on the Banana Pi (I lost > my Jetson board, need to reclaim next). That also means, GICv3 is > compile-tested only. > > Tony, if you can reintegrate you patches on top soon, I will refrain > from doing this with the current wip/arm64 state and will wait for your > test results.
Rebasing on these, after some minor touches, and it still works on the AMD Seattle. Cheers Tony > > Thorough review welcome, specifically as I started reading the related > sections in the manuals only last weekend. > > Thanks, > Jan > > Jan Kiszka (22): > arm: Use asm-defines.h for struct per_cpu members > arm: Add missing printk.h include > arm: Fix build warning in gic-v3 > arm: Remove unneeded include from irqchip.h > arm: Un-inline spi_in_cell > arm: Remove write-only priority field from pending_irq > arm: Remove maintenance flag from pending_irq.type.sgi > arm: Remove hw flag from pending_irq > arm: Remove cpuid from pending_irq > arm: Remove irq field from pending_irq > arm: Remove return code from irqchip_inject_pending > arm: Remove unused return code of irqchip_set_pending > arm: Disable maintenance interrupt on successful injection > arm: Make sure to not queue interrupt that were rejected as duplicates > arm: Convert software queue of pending interrupts into a ring > arm: Remove try_inject parameter from irqchip_set_pending > arm: Enable maintenance interrupt also from irqchip_set_pending > arm: Enable / disable maintenance interrupt in distributor > arm: Protect hypervisor used SGIs and PPIs from cell changes > arm: Make cpu_init and cpu_reset callbacks mandatory > arm: Reject unknown GIC versions > arm: Consolidate gic_irqchip to irqchip > > hypervisor/arch/arm/asm-defines.c | 12 ++ > hypervisor/arch/arm/control.c | 2 +- > hypervisor/arch/arm/entry.S | 3 +- > hypervisor/arch/arm/gic-common.c | 28 ++-- > hypervisor/arch/arm/gic-v2.c | 62 +++++---- > hypervisor/arch/arm/gic-v3.c | 65 +++++----- > hypervisor/arch/arm/include/asm/irqchip.h | 52 ++------ > hypervisor/arch/arm/include/asm/percpu.h | 36 ++--- > hypervisor/arch/arm/irqchip.c | 209 > +++++++++--------------------- > hypervisor/arch/arm/setup.c | 2 +- > hypervisor/arch/arm/smp-vexpress.c | 1 + > 11 files changed, 184 insertions(+), 288 deletions(-) > -- Antonios Motakis Virtualization Engineer Huawei Technologies Duesseldorf GmbH European Research Center Riesstrasse 25, 80992 München -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
