From: Antonios Motakis <[email protected]> Add the root cell configuration and necessary headers to build and run Jailhouse on the AMD Seattle development board.
Signed-off-by: Antonios Motakis <[email protected]> --- ci/jailhouse-config-amd-seattle.h | 5 + configs/amd-seattle.c | 169 +++++++++++++++++++++++++++ hypervisor/arch/arm/include/asm/uart_pl011.h | 2 + hypervisor/arch/arm64/include/asm/platform.h | 19 +++ 4 files changed, 195 insertions(+) create mode 100644 ci/jailhouse-config-amd-seattle.h create mode 100644 configs/amd-seattle.c diff --git a/ci/jailhouse-config-amd-seattle.h b/ci/jailhouse-config-amd-seattle.h new file mode 100644 index 0000000..c721a46 --- /dev/null +++ b/ci/jailhouse-config-amd-seattle.h @@ -0,0 +1,5 @@ +#define CONFIG_TRACE_ERROR 1 +#define CONFIG_ARM_GIC 1 +#define CONFIG_MACH_AMD_SEATTLE 1 +#define CONFIG_SERIAL_AMBA_PL011 1 +#define JAILHOUSE_BASE 0x82fc000000 diff --git a/configs/amd-seattle.c b/configs/amd-seattle.c new file mode 100644 index 0000000..a5dd5f5 --- /dev/null +++ b/configs/amd-seattle.c @@ -0,0 +1,169 @@ +/* + * Jailhouse AArch64 support + * + * Copyright (C) 2015 Huawei Technologies Duesseldorf GmbH + * + * Authors: + * Antonios Motakis <[email protected]> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include <linux/types.h> +#include <jailhouse/cell-config.h> + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) + +struct { + struct jailhouse_system header; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[16]; + struct jailhouse_irqchip irqchips[1]; +} __attribute__((packed)) config = { + .header = { + .signature = JAILHOUSE_SYSTEM_SIGNATURE, + .hypervisor_memory = { + .phys_start = 0x82fc000000, + .size = 0x4000000, + }, + .debug_console = { + .phys_start = 0xe1010000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_IO, + }, + .root_cell = { + .name = "amd-seattle", + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = 1, + }, + }, + + .cpus = { + 0xff, + }, + + .mem_regions = { + /* gpio */ { + .phys_start = 0xe0030000, + .virt_start = 0xe0030000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* gpio */ { + .phys_start = 0xe0080000, + .virt_start = 0xe0080000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* gpio */ { + .phys_start = 0xe1050000, + .virt_start = 0xe1050000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* sata */ { + .phys_start = 0xe0300000, + .virt_start = 0xe0300000, + .size = 0x10000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* xgmac */ { + .phys_start = 0xe0700000, + .virt_start = 0xe0700000, + .size = 0x100000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* xgmac */ { + .phys_start = 0xe0900000, + .virt_start = 0xe0900000, + .size = 0x100000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* smmu */ { + .phys_start = 0xe0600000, + .virt_start = 0xe0600000, + .size = 0x10000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* smmu */ { + .phys_start = 0xe0800000, + .virt_start = 0xe0800000, + .size = 0x10000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* serial */ { + .phys_start = 0xe1010000, + .virt_start = 0xe1010000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* ssp */ { + .phys_start = 0xe1020000, + .virt_start = 0xe1020000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* ssp */ { + .phys_start = 0xe1030000, + .virt_start = 0xe1030000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* phy */ { + .phys_start = 0xe1240000, + .virt_start = 0xe1240000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* phy */ { + .phys_start = 0xe1250000, + .virt_start = 0xe1250000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* ccn */ { + .phys_start = 0xe8000000, + .virt_start = 0xe8000000, + .size = 0x1000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* pcie */ { + .phys_start = 0xf0000000, + .virt_start = 0xf0000000, + .size = 0x10000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* RAM */ { + .phys_start = 0x8000000000, + .virt_start = 0x8000000000, + .size = 0x400000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE, + }, + }, + .irqchips = { + /* GIC */ { + .address = 0xe1100000, + .pin_bitmap = 0xffffffffffffffff, + }, + }, + +}; diff --git a/hypervisor/arch/arm/include/asm/uart_pl011.h b/hypervisor/arch/arm/include/asm/uart_pl011.h index 8548c86..9505161 100644 --- a/hypervisor/arch/arm/include/asm/uart_pl011.h +++ b/hypervisor/arch/arm/include/asm/uart_pl011.h @@ -70,6 +70,7 @@ static void uart_init(struct uart_chip *chip) { +#ifndef CONFIG_MACH_AMD_SEATTLE /* 115200 8N1 */ /* FIXME: Can be improved with an implementation of __aeabi_uidiv */ u32 bauddiv = UART_CLK / (16 * 115200); @@ -83,6 +84,7 @@ static void uart_init(struct uart_chip *chip) mmio_write16(base + UARTIBRD, bauddiv); mmio_write16(base + UARTCR, (UARTCR_EN | UARTCR_TXE | UARTCR_RXE | UARTCR_Out1 | UARTCR_Out2)); +#endif } static void uart_wait(struct uart_chip *chip) diff --git a/hypervisor/arch/arm64/include/asm/platform.h b/hypervisor/arch/arm64/include/asm/platform.h index f8d4d91..e97b0f9 100644 --- a/hypervisor/arch/arm64/include/asm/platform.h +++ b/hypervisor/arch/arm64/include/asm/platform.h @@ -47,4 +47,23 @@ #endif /* CONFIG_MACH_FOUNDATION_V8 */ +#ifdef CONFIG_MACH_AMD_SEATTLE + +/* the device tree shipped with the kernel is wrong; + * these are the corrected values */ +# define GICD_BASE ((void *)0xe1110000) +# define GICD_SIZE 0x1000 +# define GICC_BASE ((void *)0xe112f000) +# define GICC_SIZE 0x2000 +# define GICH_BASE ((void *)0xe1140000) +# define GICH_SIZE 0x10000 +# define GICV_BASE ((void *)0xe116f000) +# define GICV_SIZE 0x2000 + +# include <asm/gic_v2.h> +# define MAINTENANCE_IRQ 25 +# define UART_BASE 0xe1010000 + +#endif /* CONFIG_MACH_AMD_SEATTLE */ + #endif /* !_JAILHOUSE_ASM_PLATFORM_H */ -- 2.8.0.rc3 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. 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