Branch: refs/heads/next
Home: https://github.com/siemens/jailhouse
Commit: a580b652d9d70b885e2822417fce8458bcb847c5
https://github.com/siemens/jailhouse/commit/a580b652d9d70b885e2822417fce8458bcb847c5
Author: Antonios Motakis <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M driver/main.c
M hypervisor/arch/arm/include/asm/jailhouse_hypercall.h
M hypervisor/arch/x86/include/asm/jailhouse_hypercall.h
M hypervisor/setup.c
Log Message:
-----------
driver: ioremap the hypervisor firmware to any kernel address
At the moment the Linux driver maps the Jailhouse binary to
JAILHOUSE_BASE. The underlying assumption is that Linux may map the
firmware (in the Linux kernel space), to the same virtual address it
has been built to run from.
This assumption is unworkable on ARMv8 processors running in AArch64
mode. Kernel memory is allocated in a high address region, that is
not addressable from EL2, where the hypervisor will run from.
This patch removes the assumption, by introducing the
JAILHOUSE_BORROW_ROOT_PT define, which signals the behavior of the
current architectures.
We also turn the entry point in the header, into an offset from the
Jailhouse load address, so we can enter the image regardless of
where it will be mapped.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: a829b136c65180484b2645b64abd893b0622a2c1
https://github.com/siemens/jailhouse/commit/a829b136c65180484b2645b64abd893b0622a2c1
Author: Dmitry Voytik <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M driver/cell.c
M driver/main.c
Log Message:
-----------
driver: sync I-cache, D-cache and memory
Syncronize I-cache with D-cache after loading the hypervisor
image or a cell image. This must be done in arm64 according to
ARMv8 ARM spec. See page 1712, D3.4.6 "Non-cacheable accesses
and instruction caches".
This patch fixes coherency problems observed on real HW targets.
On x86 this operation is a NOP.
Signed-off-by: Dmitry Voytik <[email protected]>
Signed-off-by: Antonios Motakis <[email protected]>
[[email protected]: edited comments]
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 63bc88f473973f12031c22be60e317353c77a428
https://github.com/siemens/jailhouse/commit/63bc88f473973f12031c22be60e317353c77a428
Author: Antonios Motakis <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M hypervisor/arch/arm/lib.c
M hypervisor/arch/x86/apic.c
M hypervisor/arch/x86/control.c
M hypervisor/include/jailhouse/printk.h
M hypervisor/include/jailhouse/processor.h
M hypervisor/printk.c
Log Message:
-----------
core: make phys_processor_id() return unsigned long
32 bits ought not be enough for anybody.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 3c1f49acbf6b75f0fb3501837c7e1ef107479f97
https://github.com/siemens/jailhouse/commit/3c1f49acbf6b75f0fb3501837c7e1ef107479f97
Author: Antonios Motakis <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M hypervisor/control.c
Log Message:
-----------
core: panic_stop: print current cell only if it has been set
Currently during a panic, panic_stop will print the current cell
on the CPU where the panic occurred. However, if the hypervisor
panics sufficiently early during initialization, we may end up in
a situation where the root cell has not been initialized. This can
easily cause a trap loop, making the panic output less useful.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 69842056d00ac67f6b3a09ba116b94a6c3a2fd9d
https://github.com/siemens/jailhouse/commit/69842056d00ac67f6b3a09ba116b94a6c3a2fd9d
Author: Jan Kiszka <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/x86/include/asm/paging.h
M hypervisor/include/jailhouse/paging.h
M hypervisor/paging.c
Log Message:
-----------
core: Add support for aligned page allocation
Refactor page_alloc to page_alloc_internal which accepts an additional
constraint for its allocation: align_mask. The allocated region will now
have its start page chosen so that page_number & align_mask is zero. If
no alignment is required, align_mask just needs to be set to 0. This is
what page_alloc exploits.
However, the new function page_alloc_aligned is introduces to return
page regions aligned according to their size (num pages will be aligned
by num * PAGE_SIZE). This implied that num needs to be a power of two.
This will be used on the AArch64 port of Jailhouse to support physical
address ranges from 40 to 44 bits: in these configurations, the initial
page table level may take up multiple consecutive pages.
Based on patch by Antonios Motakis.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 260fe69f158f44a0819a2708906759195f2f922d
https://github.com/siemens/jailhouse/commit/260fe69f158f44a0819a2708906759195f2f922d
Author: Antonios Motakis <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: pass SPIs with large ids to the root cell
The current design for cell configuration files, defines the SPIs
to be passed to a cell as 64 bit bitmap. In order to use Jailhouse
on targets that have SPI ids larger than 64, we need to work
around this limitation.
Pass large SPIs to the root cell for now. A permanent solution to
this problem will need to tackle the cell configuration format.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 4276ae72471762dfe5948b5c8dfb782036d734dd
https://github.com/siemens/jailhouse/commit/4276ae72471762dfe5948b5c8dfb782036d734dd
Author: Claudio Fontana <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M hypervisor/arch/arm/lib.c
M hypervisor/lib.c
Log Message:
-----------
core: lib: replace ARM memcpy implementation with generic version
Remove the memcpy implementation from the ARM port, and add a
generic version to the core library for all architectures.
Signed-off-by: Claudio Fontana <[email protected]>
Signed-off-by: Antonios Motakis <[email protected]>
[[email protected]: removed all signs of weakness!]
Signed-off-by: Jan Kiszka <[email protected]>
Commit: c144ef6a8a9cabb38986878dd9ebf72a0be818d1
https://github.com/siemens/jailhouse/commit/c144ef6a8a9cabb38986878dd9ebf72a0be818d1
Author: Antonios Motakis <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/control.h
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm/lib.c
M hypervisor/arch/arm/psci.c
M hypervisor/arch/arm/setup.c
Log Message:
-----------
arm: psci: support multiple affinity levels in MPIDR
PSCI actually takes CPU parameters by the MPIDR id, which may
differ from the logical id of the CPU. This patch is the first step
into properly handling the CPU affinity levels in the MPIDR.
Signed-off-by: Antonios Motakis <[email protected]>
[Jan: add missing processor.h include to setup.c]
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 2485703d42de06690c7937b0ff3de3023f747da2
https://github.com/siemens/jailhouse/commit/2485703d42de06690c7937b0ff3de3023f747da2
Author: Antonios Motakis <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/psci.h
M hypervisor/arch/arm/traps.c
Log Message:
-----------
arm: replace IS_PSCI_FN macro with more explicit versions
The previous version of the macro allows for more false positives
than necessary.
Replace the macro with IS_PSCI_32 and IS_PSCI_UBOOT macros, that
explicitly check for the 32 bit PSCI IDs, and the PSCI 0.1 IDs
used by uboot. ARMv8 will need an additinal check for the IDs
of 64 bit PSCI functions.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 6996c52cb359ad204b403918bb54fe22e7accc74
https://github.com/siemens/jailhouse/commit/6996c52cb359ad204b403918bb54fe22e7accc74
Author: Antonios Motakis <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/gic_common.h
Log Message:
-----------
arm: move the handle_irq_route function to the GICv3 module
The handle_irq_route function is not needed with the GICv2.
On the ARMv8 port we will not assign a virt_id to each CPU,
opting to use the MPIDR as much as we can from the start.
GICv3 will need heavier refactoring for this purpose; by moving
this function we can reuse the GICv2 code on ARMv8.
Signed-off-by: Antonios Motakis <[email protected]>
[Jan: implement stub in v2 to reduce #ifdefs]
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 27c3556a711ed9f463cdd69bd406b16ac7b793c8
https://github.com/siemens/jailhouse/commit/27c3556a711ed9f463cdd69bd406b16ac7b793c8
Author: Antonios Motakis <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/include/asm/paging_modes.h
M hypervisor/arch/arm/mmu_cell.c
M hypervisor/arch/arm/paging.c
Log Message:
-----------
arm: prepare port for 48 bit PARange support
We currently support 3 levels of page tables for a 39 bits PA range
on ARM. This patch implements support for 4 level page tables,
and 3 level page tables with a concatenated level 1 root page
table.
On AArch32 we stick with the current restriction of building for
a 39 bit physical address space; however this change will allow
us to support a 40 to 48 bit PARange on AArch64.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 3449fc62f82a478450d05fd954e2025eb55a50e6
https://github.com/siemens/jailhouse/commit/3449fc62f82a478450d05fd954e2025eb55a50e6
Author: Antonios Motakis <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/mmu_cell.c
Log Message:
-----------
arm: put the value of VTCR for cells in a define
We can reuse the code under hypervisor/arch/arm/mmu_cell.c for the
AArch64 port, save for the value we use for the VTCRL. AArch64 will
need in addition to the flags set by the AArch32 port, to set the
size of the address space.
We put this behind a define in asm/paging.h to allow this reuse.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: eca3bab8f8e31f8fd3273b773c48e1374a76c07a
https://github.com/siemens/jailhouse/commit/eca3bab8f8e31f8fd3273b773c48e1374a76c07a
Author: Antonios Motakis <[email protected]>
Date: 2016-06-23 (Thu, 23 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/processor.h
M hypervisor/arch/arm/mmu_cell.c
Log Message:
-----------
arm: hide TLB flush behind a macro
Hide TLB flushes issues by the MMU code behind a macro, so we can
increase our chances of reusing some of this code.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Compare:
https://github.com/siemens/jailhouse/compare/7d68082e71d8...eca3bab8f8e3
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