On Tuesday, June 21, 2016 at 11:22:53 PM UTC+5:30, J. Kiszka wrote: > On 2016-06-21 19:00, [email protected] wrote: > > hi, > > I am working on banana pi board. I am able to run the FreeRTOS in non root > > cell with provided configuration. i tested UART7 interrupt and its is > > working fine. i tried extended the main.c for supporting CAN interrupt. But > > i am getting some hypervisor exception while accessing ITARGETSR with CAN > > interrupt number 58. i am sharing the code part which i used for can > > interrupt enable. Please let me know which part i did wrong. > > > > #define CAN0_IRQ 58 > > > > static void can_irq_enable(void) > > { > > volatile uint8_t *gicd = gic_v2_gicd_get_address() + GICD_ITARGETSR; > > int n, m, offset; > > m = CAN0_IRQ; > > printf("CAN gicd=%p CPUID=%d\n", gicd, (int)gicd[0]); > > n = m / 4; > > offset = 4*n; > > offset+= m % 4; > > printf("Orig GICD_ITARGETSR[%d]=%d\n",m, (int)gicd[offset]); /*--> @ this > > point i am getting exception */ > > gicd[offset] |= gicd[0]; > > printf("New GICD_ITARGETSR[%d]=%d\n",m, (int)gicd[offset]); > > gic_v2_irq_set_prio(CAN0_IRQ, portLOWEST_USABLE_INTERRUPT_PRIORITY); > > gic_v2_irq_enable(CAN0_IRQ); > > } > > > > Exception Details > > ****************************** > > Started cell "FreeRTOS" > > jailhouse@Olimex_RBEI:~/jailhouse_freeRTOS$ Unhandled HYP data abort exit > > at 0xf0002eb8 > > r0: 0x01c81000 r1: 0xf0010f5c r2: 0x00000004 r3: 0x00000943 > > r4: 0x00000943 r5: 0xf0010f5c r6: 0x00000000 r7: 0x00000003 > > r8: 0xf000d074 r9: 0xf003a000 r10: 0xf000d080 r11: 0xf000e000 > > r12: 0xf003b020 r13: 0xf0005b90 > > Physical address: 0x01c81943 ESR: 0x94000021 > > Stopping CPU 1 (Cell: "FreeRTOS") > > > > I have configured GIC for Non root cell in cell configuration as below > > > > .irqchips = { > > /* GIC */ { > > .address = 0x01c80000, > > /* Interrupt of UART 7 belongs to the client */ > > .pin_bitmap = (1ULL<<(52-32)| 1ULL<<(58-32)), > > }, > > > > > > We seem to have some bug in the hypervisor handling logic. Could you > instrument handle_irq_target in hypervisor/arch/arm/gic-common.c to see > what kind of accesses are performed? > > This line looks suspicious: > > u32 itargetsr = > mmio_read32(gicd_base + GICD_ITARGETSR + reg + offset); > > Not sure if we are allowed to do a 32-bit access on unaligned addresses > (offset % 4 != 0). If not, then the code needs a rework. > > Jan > > -- > Siemens AG, Corporate Technology, CT RDA ITP SES-DE > Corporate Competence Center Embedded Linux
Hi Jan, Thanks for your reply. I tried running the code with your patch. But for the above code which i posted,i am not getting the interrupt enabled for the CAN. For the above code with IRQ =52 (m=52), i am geting below output UART gicd=0x01c81800 CPUID=2 Orig GICD_ITARGETSR[52]=2 New GICD_ITARGETSR[52]=2 IRQ52 prio original: 0xe0 IRQ52 prio readback after 0xff: 0xf0 IRQ52 prio modified: 0xe0 and for IRQ=58, i am getting the below output CAN gicd=0x01c81800 CPUID=2 Orig GICD_ITARGETSR[58]=2 New GICD_ITARGETSR[58]=2 IRQ58 prio original: 0x0 IRQ58 prio readback after 0xff: 0x0 IRQ58 prio modified: 0x0 here i am not getting the CAN interrupt enabled and no priority is set. do i need to enable any thing additionally..? -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
