Branch: refs/heads/coverity_scan
Home: https://github.com/siemens/jailhouse
Commit: eda93050c75d3f3ef4509d3faccc451b0946b607
https://github.com/siemens/jailhouse/commit/eda93050c75d3f3ef4509d3faccc451b0946b607
Author: Antonios Motakis <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M driver/main.c
M hypervisor/arch/arm/include/asm/jailhouse_hypercall.h
M hypervisor/arch/x86/include/asm/jailhouse_hypercall.h
M hypervisor/setup.c
Log Message:
-----------
driver: ioremap the hypervisor firmware to any kernel address
At the moment the Linux driver maps the Jailhouse binary to
JAILHOUSE_BASE. The underlying assumption is that Linux may map the
firmware (in the Linux kernel space), to the same virtual address it
has been built to run from.
This assumption is unworkable on ARMv8 processors running in AArch64
mode. Kernel memory is allocated in a high address region, that is
not addressable from EL2, where the hypervisor will run from.
This patch removes the assumption, by introducing the
JAILHOUSE_BORROW_ROOT_PT define, which signals the behavior of the
current architectures.
We also turn the entry point in the header, into an offset from the
Jailhouse load address, so we can enter the image regardless of
where it will be mapped.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 37f0f7e117964c0c24a67485d3e8ca4781fab734
https://github.com/siemens/jailhouse/commit/37f0f7e117964c0c24a67485d3e8ca4781fab734
Author: Dmitry Voytik <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M driver/cell.c
M driver/main.c
Log Message:
-----------
driver: sync I-cache, D-cache and memory
Syncronize I-cache with D-cache after loading the hypervisor
image or a cell image. This must be done in arm64 according to
ARMv8 ARM spec. See page 1712, D3.4.6 "Non-cacheable accesses
and instruction caches".
This patch fixes coherency problems observed on real HW targets.
On x86 this operation is a NOP.
Signed-off-by: Dmitry Voytik <[email protected]>
Signed-off-by: Antonios Motakis <[email protected]>
[[email protected]: edited comments]
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 49a683f3a3823a445d88a2021dc69993d6edff8b
https://github.com/siemens/jailhouse/commit/49a683f3a3823a445d88a2021dc69993d6edff8b
Author: Antonios Motakis <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/lib.c
M hypervisor/arch/x86/apic.c
M hypervisor/arch/x86/control.c
M hypervisor/include/jailhouse/printk.h
M hypervisor/include/jailhouse/processor.h
M hypervisor/printk.c
Log Message:
-----------
core: make phys_processor_id() return unsigned long
32 bits ought not be enough for anybody.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 11cc0e0cf21d53544bfe19977af1520981769e34
https://github.com/siemens/jailhouse/commit/11cc0e0cf21d53544bfe19977af1520981769e34
Author: Antonios Motakis <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/control.c
Log Message:
-----------
core: panic_stop: print current cell only if it has been set
Currently during a panic, panic_stop will print the current cell
on the CPU where the panic occurred. However, if the hypervisor
panics sufficiently early during initialization, we may end up in
a situation where the root cell has not been initialized. This can
easily cause a trap loop, making the panic output less useful.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 6b74f910dc248be969f16dc57e12412412f41b36
https://github.com/siemens/jailhouse/commit/6b74f910dc248be969f16dc57e12412412f41b36
Author: Jan Kiszka <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/x86/include/asm/paging.h
M hypervisor/include/jailhouse/paging.h
M hypervisor/paging.c
Log Message:
-----------
core: Add support for aligned page allocation
Refactor page_alloc to page_alloc_internal which accepts an additional
constraint for its allocation: align_mask. The allocated region will now
have its start page chosen so that page_number & align_mask is zero. If
no alignment is required, align_mask just needs to be set to 0. This is
what page_alloc exploits.
However, the new function page_alloc_aligned is introduces to return
page regions aligned according to their size (num pages will be aligned
by num * PAGE_SIZE). This implied that num needs to be a power of two.
This will be used on the AArch64 port of Jailhouse to support physical
address ranges from 40 to 44 bits: in these configurations, the initial
page table level may take up multiple consecutive pages.
Based on patch by Antonios Motakis.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: af24262ac5020eda9da14db3ab2e84f8297fd4a2
https://github.com/siemens/jailhouse/commit/af24262ac5020eda9da14db3ab2e84f8297fd4a2
Author: Claudio Fontana <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/lib.c
M hypervisor/lib.c
Log Message:
-----------
core: lib: replace ARM memcpy implementation with generic version
Remove the memcpy implementation from the ARM port, and add a
generic version to the core library for all architectures.
Signed-off-by: Claudio Fontana <[email protected]>
Signed-off-by: Antonios Motakis <[email protected]>
[[email protected]: removed all signs of weakness!]
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 6936d5c860976325b6cd4e2fb30f251db0f133fd
https://github.com/siemens/jailhouse/commit/6936d5c860976325b6cd4e2fb30f251db0f133fd
Author: Antonios Motakis <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/control.h
M hypervisor/arch/arm/include/asm/percpu.h
M hypervisor/arch/arm/lib.c
M hypervisor/arch/arm/psci.c
M hypervisor/arch/arm/setup.c
Log Message:
-----------
arm: psci: support multiple affinity levels in MPIDR
PSCI actually takes CPU parameters by the MPIDR id, which may
differ from the logical id of the CPU. This patch is the first step
into properly handling the CPU affinity levels in the MPIDR.
Signed-off-by: Antonios Motakis <[email protected]>
[Jan: add missing processor.h include to setup.c]
Signed-off-by: Jan Kiszka <[email protected]>
Commit: f404b89d34d44bd23dba889d495564c1fbed992d
https://github.com/siemens/jailhouse/commit/f404b89d34d44bd23dba889d495564c1fbed992d
Author: Antonios Motakis <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/psci.h
M hypervisor/arch/arm/traps.c
Log Message:
-----------
arm: replace IS_PSCI_FN macro with more explicit versions
The previous version of the macro allows for more false positives
than necessary.
Replace the macro with IS_PSCI_32 and IS_PSCI_UBOOT macros, that
explicitly check for the 32 bit PSCI IDs, and the PSCI 0.1 IDs
used by uboot. ARMv8 will need an additinal check for the IDs
of 64 bit PSCI functions.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: bdcdd89e2e4f4aa439935539bb62e0c9fbaf824d
https://github.com/siemens/jailhouse/commit/bdcdd89e2e4f4aa439935539bb62e0c9fbaf824d
Author: Antonios Motakis <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/gic_common.h
Log Message:
-----------
arm: move the handle_irq_route function to the GICv3 module
The handle_irq_route function is not needed with the GICv2.
On the ARMv8 port we will not assign a virt_id to each CPU,
opting to use the MPIDR as much as we can from the start.
GICv3 will need heavier refactoring for this purpose; by moving
this function we can reuse the GICv2 code on ARMv8.
Signed-off-by: Antonios Motakis <[email protected]>
[Jan: implement stub in v2 to reduce #ifdefs]
Signed-off-by: Jan Kiszka <[email protected]>
Commit: b2b588833a6e9ade955a723242072120de9f1354
https://github.com/siemens/jailhouse/commit/b2b588833a6e9ade955a723242072120de9f1354
Author: Antonios Motakis <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/include/asm/paging_modes.h
M hypervisor/arch/arm/mmu_cell.c
M hypervisor/arch/arm/paging.c
Log Message:
-----------
arm: prepare port for 48 bit PARange support
We currently support 3 levels of page tables for a 39 bits PA range
on ARM. This patch implements support for 4 level page tables,
and 3 level page tables with a concatenated level 1 root page
table.
On AArch32 we stick with the current restriction of building for
a 39 bit physical address space; however this change will allow
us to support a 40 to 48 bit PARange on AArch64.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 0c0a0086c1deabf39aad0d3f0320da2874603139
https://github.com/siemens/jailhouse/commit/0c0a0086c1deabf39aad0d3f0320da2874603139
Author: Antonios Motakis <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/mmu_cell.c
Log Message:
-----------
arm: put the value of VTCR for cells in a define
We can reuse the code under hypervisor/arch/arm/mmu_cell.c for the
AArch64 port, save for the value we use for the VTCRL. AArch64 will
need in addition to the flags set by the AArch32 port, to set the
size of the address space.
We put this behind a define in asm/paging.h to allow this reuse.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 89b3eb4ad43eb453b7c5d782f150a68e5b6dbec6
https://github.com/siemens/jailhouse/commit/89b3eb4ad43eb453b7c5d782f150a68e5b6dbec6
Author: Antonios Motakis <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/processor.h
M hypervisor/arch/arm/mmu_cell.c
Log Message:
-----------
arm: hide TLB flush behind a macro
Hide TLB flushes issues by the MMU code behind a macro, so we can
increase our chances of reusing some of this code.
Signed-off-by: Antonios Motakis <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: c75977ab419f15af28aa57a03dcc2dccdec62428
https://github.com/siemens/jailhouse/commit/c75977ab419f15af28aa57a03dcc2dccdec62428
Author: Jan Kiszka <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/irqchip.h
Log Message:
-----------
arm: Remove unused struct pending_irq
Leftover of 8b121b498b.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: d99b6e21844e3c99b7195346a08611b3cd46a057
https://github.com/siemens/jailhouse/commit/d99b6e21844e3c99b7195346a08611b3cd46a057
Author: Jan Kiszka <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M configs/bananapi.c
M configs/f2a88xm-hd3.c
M configs/h87i.c
M configs/imb-a180.c
M configs/ioapic-demo.c
M configs/jetson-tk1.c
M configs/qemu-vm.c
M configs/vexpress-linux-demo.c
M configs/vexpress.c
M hypervisor/arch/arm/irqchip.c
M hypervisor/arch/x86/ioapic.c
M hypervisor/include/jailhouse/cell-config.h
M tools/root-cell-config.c.tmpl
Log Message:
-----------
config, core: Improve irqchip configuration
This aims at supporting irqchips with more than 64 pins. The idea is to
use multiple entries in this case, each describing a distinct set of the
pins. Therefore, a pin_base field is introduced to jailhouse_irqchip.
Moreover, we expand the number of pins for each entry to 128.
We do not exploit the extended pin number on ARM yet, but stick with
64 pins for now. Succeeding change sets will tackle it.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: f2931b157d70e7257da839588cb2a325dc2a0aa6
https://github.com/siemens/jailhouse/commit/f2931b157d70e7257da839588cb2a325dc2a0aa6
Author: Jan Kiszka <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/include/asm/cell.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Use full bitmap to manage per-cell interrupt access
Commit: 85783c01aa07f911c6eab0f53536a82a7d207f2f
https://github.com/siemens/jailhouse/commit/85783c01aa07f911c6eab0f53536a82a7d207f2f
Author: Jan Kiszka <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M configs/bananapi.c
M configs/vexpress-linux-demo.c
M configs/vexpress.c
Log Message:
-----------
config: Correct / comment GIC irqchip addresses
We will soon evaluate them, so their correct value starts to matter.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: d14d1703a7f285a93fde6d3198ab639ec72bb0b8
https://github.com/siemens/jailhouse/commit/d14d1703a7f285a93fde6d3198ab639ec72bb0b8
Author: Jan Kiszka <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
Log Message:
-----------
arm: Rename reg parameter of handle_irq_target to irq
Reflects better what this is about.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: b7857f0e03f4caea5b383a5722ce653bfd7e8ad5
https://github.com/siemens/jailhouse/commit/b7857f0e03f4caea5b383a5722ce653bfd7e8ad5
Author: Jan Kiszka <[email protected]>
Date: 2016-06-26 (Sun, 26 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
Log Message:
-----------
arm: Print IRQ number rather than SPI on handle_irq_target errors
Configuration and other reportings are based on absolute IDs as well.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 902ee9cfd32652f6926da709b259d46a68bdebf4
https://github.com/siemens/jailhouse/commit/902ee9cfd32652f6926da709b259d46a68bdebf4
Author: Jan Kiszka <[email protected]>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Rework spi_in_cell to irqchip_irq_in_cell
Make use of the the fully populated irq_bitmap and enhance spi_in_cell
to consider SGIs and PPIs as well. This allows to simplify
restrict_bitmask_access.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: ddc4a66cfa509b422a5c385783d2e863c7f875dd
https://github.com/siemens/jailhouse/commit/ddc4a66cfa509b422a5c385783d2e863c7f875dd
Author: Jan Kiszka <[email protected]>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/include/jailhouse/control.h
Log Message:
-----------
core: Introduce first_cpu
Extracted from patch of Antonios Motakis: Avoid the barely readable
"for_each_cpu(...) break;" pattern.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: da2bcc4252b488ad0740df9af6e2a5a90bc4f164
https://github.com/siemens/jailhouse/commit/da2bcc4252b488ad0740df9af6e2a5a90bc4f164
Author: Jan Kiszka <[email protected]>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Remove SPI target reset on cell destruction
There is no point in updating the SPI routing on cell destruction: all
CPUs the cell owned will be given back to the root cell. So any
previously written valid target configuration remain valid.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: a70819d9adfb29cd096c3ef2e8cafe83a8ff21e1
https://github.com/siemens/jailhouse/commit/a70819d9adfb29cd096c3ef2e8cafe83a8ff21e1
Author: Jan Kiszka <[email protected]>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/control.c
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Fold irqchip_root_cell_shrink into irqchip_cell_init
Simplifies the code.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 0456bcecbe7d4b1ca159f996a7706c3ec6e3391c
https://github.com/siemens/jailhouse/commit/0456bcecbe7d4b1ca159f996a7706c3ec6e3391c
Author: Jan Kiszka <[email protected]>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/include/asm/gic_common.h
Log Message:
-----------
arm: Factor out gic_targets_in_cell
We will reuse it for affinity adjustments on cell creation.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 90e7060810f2adab5b7646150b9f465014855ed1
https://github.com/siemens/jailhouse/commit/90e7060810f2adab5b7646150b9f465014855ed1
Author: Jan Kiszka <[email protected]>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-v3.c
Log Message:
-----------
arm: Validate ARE-NS being enabled with GICv3
Linux does enable Affinity Routing, but better check because the code
depends on this.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 011ab917a15057f52d36b1542bf3454abec55160
https://github.com/siemens/jailhouse/commit/011ab917a15057f52d36b1542bf3454abec55160
Author: Jan Kiszka <[email protected]>
Date: 2016-06-27 (Mon, 27 Jun 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
M hypervisor/arch/arm/gic-v2.c
M hypervisor/arch/arm/gic-v3.c
M hypervisor/arch/arm/include/asm/gic_common.h
M hypervisor/arch/arm/include/asm/irqchip.h
M hypervisor/arch/arm/irqchip.c
Log Message:
-----------
arm: Rework interrupt affinity management on cell creation
So far, we only ensured that the affinities of interrupts given to new
cells match with the corresponding CPU set. However, we also need to
check that Linux properly adjusted the affinity of all its remaining
interrupts properly.
This introduces a new irqchip callback adjust_irq_target which performs
the check and the potential adjustment to the first CPU of a cell on a
per-interrupt basis. A single loop in irqchip_cell_init triggers them.
gic_target_spis and gic_route_spis become obsolete.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 51f3bdab18fe814430b7d01886494f532d9f4566
https://github.com/siemens/jailhouse/commit/51f3bdab18fe814430b7d01886494f532d9f4566
Author: Jan Kiszka <[email protected]>
Date: 2016-06-28 (Tue, 28 Jun 2016)
Changed paths:
M tools/jailhouse-config-create
Log Message:
-----------
tools: config-create: Do not enter infinite over disabled PCI devices
If a PCI device is disabled, e.g. a secondary GPU, we may not see its
config space anymore while it is still listed. With config all 0xff, we
will then enter an infinite loop while trying to make sense of the
capability list. Prevent this, issuing a warning that we will skip this
device.
Reported-by: Thomas Pettinger <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 5ccf77738bab763691a965177f1346e79f262c75
https://github.com/siemens/jailhouse/commit/5ccf77738bab763691a965177f1346e79f262c75
Author: Jan Kiszka <[email protected]>
Date: 2016-07-05 (Tue, 05 Jul 2016)
Changed paths:
M hypervisor/arch/arm/control.c
Log Message:
-----------
arm: Remove duplicate register resets
Signed-off-by: Jan Kiszka <[email protected]>
Commit: d8e6c3091b4ce50a06cb0e20a7e4105aebb4be97
https://github.com/siemens/jailhouse/commit/d8e6c3091b4ce50a06cb0e20a7e4105aebb4be97
Author: Jan Kiszka <[email protected]>
Date: 2016-07-05 (Tue, 05 Jul 2016)
Changed paths:
M hypervisor/arch/x86/vtd.c
M tools/jailhouse-hardware-check
Log Message:
-----------
x86: Officially support VT-d Caching Mode != 0
We already flush all domain-related caches after reconfigurations,
irrespective of the address ranges changed and how they were changed
(made valid or invalid). So the feature check during unit setup is
actually superfluous - remove it.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 71744b9aaa406f9521d4d2d83593b4851002f0f7
https://github.com/siemens/jailhouse/commit/71744b9aaa406f9521d4d2d83593b4851002f0f7
Author: Jan Kiszka <[email protected]>
Date: 2016-07-08 (Fri, 08 Jul 2016)
Changed paths:
M hypervisor/arch/x86/include/asm/processor.h
M hypervisor/arch/x86/include/asm/vmx.h
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: vmx: Enable INVPCID if reported via CPUID
Linux kernel 4.6 and later make use of this instruction and crash if we
do not allow it. It flushes TLB mappings, but only on the caller's
logical CPU.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 44bf273bf2819398270eb96e864d9d6e865297e5
https://github.com/siemens/jailhouse/commit/44bf273bf2819398270eb96e864d9d6e865297e5
Author: Jan Kiszka <[email protected]>
Date: 2016-07-17 (Sun, 17 Jul 2016)
Changed paths:
M hypervisor/arch/arm/gic-common.c
Log Message:
-----------
arm: Fix corruption of protected bits in restrict_bitmask_access
We must only mask in bits that are permitted according to access_mask.
The current code cause troubles to the root cell when a non-root Linux
instance was booting.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: ce91712ea2b18e139092aed3a1a3891bda63f4c2
https://github.com/siemens/jailhouse/commit/ce91712ea2b18e139092aed3a1a3891bda63f4c2
Author: Jan Kiszka <[email protected]>
Date: 2016-07-17 (Sun, 17 Jul 2016)
Changed paths:
M configs/ivshmem-demo.c
M configs/linux-x86-demo.c
M configs/qemu-vm.c
Log Message:
-----------
configs: Expand ivshmem regions to 1 MB
More space helps with throughput when using the shared memory for
inter-cell networking.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 77c0678dd88ceb64cd00347a7ba2ac1fd4aed9ae
https://github.com/siemens/jailhouse/commit/77c0678dd88ceb64cd00347a7ba2ac1fd4aed9ae
Author: Jan Kiszka <[email protected]>
Date: 2016-07-17 (Sun, 17 Jul 2016)
Changed paths:
M hypervisor/arch/x86/control.c
M hypervisor/include/jailhouse/control.h
Log Message:
-----------
core: Required CPU to be stopped prior to calling arch_shutdown_cpu
This is what shutdown, the only caller, always does and what the ARM
implementation already assumes.
Commit: 9a6e4870b216658077ce1f62851ece7f579f2b29
https://github.com/siemens/jailhouse/commit/9a6e4870b216658077ce1f62851ece7f579f2b29
Author: Jan Kiszka <[email protected]>
Date: 2016-07-17 (Sun, 17 Jul 2016)
Changed paths:
M driver/cell.c
M driver/cell.h
Log Message:
-----------
driver: Make a bunch of cell functions static
jailhouse_cell_create, jailhouse_cell_register, jailhouse_cell_delete -
none of these is used outside of cell.c. Make them static.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: a15ddc3b506a66aa78cdf5fd5500812b495cec80
https://github.com/siemens/jailhouse/commit/a15ddc3b506a66aa78cdf5fd5500812b495cec80
Author: Jan Kiszka <[email protected]>
Date: 2016-07-17 (Sun, 17 Jul 2016)
Changed paths:
M driver/cell.c
M driver/cell.h
M driver/main.c
Log Message:
-----------
driver: Destroy non-root cells before disabling the hypervisor
The hypervisor's disable function will lose support for destroying
non-root cells along with the shutdown. Prepare for this by performing
an explicit non-root cell destruction prior to calling the shutdown
command.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: e9060322fedd18d343338fcabbb96b6285d36262
https://github.com/siemens/jailhouse/commit/e9060322fedd18d343338fcabbb96b6285d36262
Author: Jan Kiszka <[email protected]>
Date: 2016-07-17 (Sun, 17 Jul 2016)
Changed paths:
M Documentation/hypervisor-interfaces.txt
M hypervisor/control.c
Log Message:
-----------
core: Deny shutdown with still existing non-root cells
Simplify the shutdown logic by requiring the root cell driver to
explicitly destroy all non-root cells first. In particular, it helps to
resolve the tricky handover of non-root cell CPUs in unplugged state to
Linux.
At this chance, properly document potential races around the shutdown
and other management hypercalls. They are non-obvious but harmless for
the integrity of any non-root cell.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 9613f81a7d993b8fab6f3edf3e2ecdbcd3f18abe
https://github.com/siemens/jailhouse/commit/9613f81a7d993b8fab6f3edf3e2ecdbcd3f18abe
Author: Jan Kiszka <[email protected]>
Date: 2016-07-17 (Sun, 17 Jul 2016)
Changed paths:
M hypervisor/arch/arm/control.c
M hypervisor/arch/x86/control.c
M hypervisor/arch/x86/include/asm/percpu.h
M hypervisor/include/jailhouse/control.h
Log Message:
-----------
x86, arm: Remove unused arch_shutdown_cpu
Now that we no longer need to shut down non-root CPUs directly, we can
get rid of this arch function. On x86, it also allows the removal of
per_cpu::shutdown_cpu and related handling. On ARM, we can drop the
PSCI_CPU_OFF call from arch_reset_self and the irqchip_cell_exit for
non-root cells from arch_shutdown.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 6d7ac3d3f5361058f860cb992baafb30451f70a5
https://github.com/siemens/jailhouse/commit/6d7ac3d3f5361058f860cb992baafb30451f70a5
Author: Jan Kiszka <[email protected]>
Date: 2016-07-17 (Sun, 17 Jul 2016)
Changed paths:
M hypervisor/mmio.c
Log Message:
-----------
core: Fix printing of invalid MMIO accesses
mem->phys_start is u64, but we only print up to unsigned long. Adjust
the input type. Resolves broken size reports on 32-bit ARM.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 014e86ec2882e6b7722a043879a00dcef143fccb
https://github.com/siemens/jailhouse/commit/014e86ec2882e6b7722a043879a00dcef143fccb
Author: Jan Kiszka <[email protected]>
Date: 2016-07-17 (Sun, 17 Jul 2016)
Changed paths:
M driver/cell.c
Log Message:
-----------
driver: Gracefully handle zero-sized load requests
We currently fail if a load request has a size of 0, because mapping an
empty region fails. While such requests are often caused by corrupted
files there may also be valid use cases. So better handle this
gracefully.
Signed-off-by: Jan Kiszka <[email protected]>
Compare:
https://github.com/siemens/jailhouse/compare/7287a5a75cab...014e86ec2882
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