Hi all,
I'd like to have some word by an expert on what we have to do in
Jailhouse when changing the stage-2 page tables. This is what currently
happens for 32-bit ARM (maybe Tony can add a word on potential
deviations for ARM64):
- all affected CPUs, except the one executing the changes, are put in
an busy-wait loop
- we modify the page tables, i.e. we directly write the desired state
on the executing CPU
- we resume the CPUs, and that triggers
- TLBs flushes (TLBIALL) on CPUs affected by the changes
- in some cases also dcache flushes
I've two questions for a while now:
- Are dcache flushes consistently required, or does the MMU snoop
caches when doing stage-2 translations? We could easily add a
DCCIMVAC for the modified entries, but I saw KVM flushing even
page-wise.
- Under which conditions do we need to apply [1] ("break before make")
in our setup? Is it really required to first write an invalid
PTE/PMD/etc., then flush TLBs on all affected CPUs, and only then
write the new entries?
Any insights welcome (including potential references to ARM ARM sections
so that we can document this in the code)!
Thanks,
Jan
[1] http://thread.gmane.org/gmane.comp.emulators.kvm.arm.devel/6244
--
Siemens AG, Corporate Technology, CT RDA ITP SES-DE
Corporate Competence Center Embedded Linux
--
You received this message because you are subscribed to the Google Groups
"Jailhouse" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to [email protected].
For more options, visit https://groups.google.com/d/optout.
