On 2016-06-17 21:12, [email protected] wrote:
> From: Antonios Motakis <[email protected]>
>
> The AArch64 page table format is very similar, almost identical to
> the AArch32 page table format. Add a header file for the AArch64 page
> table format, based on the AArch32 implementation.
>
> AArch64 introduces an extra level of page tables, for a total of
> four, and support for different translation granule sizes.
> Sticking to a granule size of 4Kb, we end up with an identical page
> table format to AArch32. Using either 3 or the full 4 supported
> levels of page tables, we can reach a physical address range of
> 48 bits.
>
> Signed-off-by: Antonios Motakis <[email protected]>
> ---
> hypervisor/arch/arm64/include/asm/paging.h | 245
> +++++++++++++++++++++++++++++
> 1 file changed, 245 insertions(+)
> create mode 100644 hypervisor/arch/arm64/include/asm/paging.h
>
> diff --git a/hypervisor/arch/arm64/include/asm/paging.h
> b/hypervisor/arch/arm64/include/asm/paging.h
> new file mode 100644
> index 0000000..2d20bc3
> --- /dev/null
> +++ b/hypervisor/arch/arm64/include/asm/paging.h
...
> +
> +/* Only executed on hypervisor paging struct changes */
> +static inline void arch_paging_flush_page_tlbs(unsigned long page_addr)
> +{
> + asm volatile("tlbi vae2, %0\n"
> + : : "r" (page_addr >> PAGE_SHIFT));
> +}
> +
I could use a good explanation (for a commit log) why I need this
diff --git a/hypervisor/arch/arm64/include/asm/paging.h
b/hypervisor/arch/arm64/include/asm/paging.h
index 2d17acd..76804e0 100644
--- a/hypervisor/arch/arm64/include/asm/paging.h
+++ b/hypervisor/arch/arm64/include/asm/paging.h
@@ -258,8 +258,11 @@ static inline void arm_paging_vcpu_flush_tlbs(void)
/* Only executed on hypervisor paging struct changes */
static inline void arch_paging_flush_page_tlbs(unsigned long page_addr)
{
- asm volatile("tlbi vae2, %0\n"
- : : "r" (page_addr >> PAGE_SHIFT));
+ asm volatile(
+ "dsb ishst\n\t"
+ "tlbi vae2, %0\n\t"
+ "dsb ish\n\t"
+ : : "r" (page_addr >> PAGE_SHIFT));
}
/* Used to clean the PAGE_MAP_COHERENT page table changes */
on the Hi6220 to use the hypervisor mappings reliably. Without it, the
access to the first device mapping (GICD) fails. It's not needed on the
AMD Opteron, though.
And we don't have such barriers on 32-bit ARM.
Thanks,
Jan
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