Branch: refs/heads/master
  Home:   https://github.com/siemens/jailhouse
  Commit: 8d9caf596ab4d640fa272cb4c33b50e1df16c211
      
https://github.com/siemens/jailhouse/commit/8d9caf596ab4d640fa272cb4c33b50e1df16c211
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M hypervisor/arch/arm/irqchip.c

  Log Message:
  -----------
  arm: Avoid assignment in if clause

Better readability, less risk to confuse with comparisons.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 4b27cac4c910f2dfba0041b5fdf962766fa57d9f
      
https://github.com/siemens/jailhouse/commit/4b27cac4c910f2dfba0041b5fdf962766fa57d9f
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M hypervisor/arch/arm/irqchip.c

  Log Message:
  -----------
  arm: Assume irqchip init function is available

Having no init function for the irqchip is a programming error, not a
runtime issue.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: e9466d272e6f9ea5cd1ef5411804ff2d09b4afd4
      
https://github.com/siemens/jailhouse/commit/e9466d272e6f9ea5cd1ef5411804ff2d09b4afd4
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M hypervisor/arch/arm/irqchip.c

  Log Message:
  -----------
  arm: Rework no-GICD-case in irqchip_init

If we fail here, the hypervisor cannot be initialized. So there is no
point in (partial) rollback. Furthermore, replace the explicit error
message with proper trace_error.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: a5d1415f3cb2706731eb28b26e5e4f835ed87858
      
https://github.com/siemens/jailhouse/commit/a5d1415f3cb2706731eb28b26e5e4f835ed87858
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M ci/jailhouse-config-banana-pi.h
    M ci/jailhouse-config-vexpress.h
    M hypervisor/arch/arm/Makefile
    M inmates/lib/arm/Makefile

  Log Message:
  -----------
  arm: Rename CONFIG_ARM_GIC to CONFIG_ARM_GIC_V2

Makes it clearer what this is selecting.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: bfa8093154021c9cc4970b20baf0da7b6e425a95
      
https://github.com/siemens/jailhouse/commit/bfa8093154021c9cc4970b20baf0da7b6e425a95
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M ci/jailhouse-config-vexpress.h

  Log Message:
  -----------
  ci: Build vexpress with GICv3

Ensures that we build-test the GICv3 code as well.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: e9c38ea5eee50189f292fdf56825a2a7ecb5635d
      
https://github.com/siemens/jailhouse/commit/e9c38ea5eee50189f292fdf56825a2a7ecb5635d
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M hypervisor/arch/arm/gic-common.c
    M hypervisor/arch/arm/gic-v2.c
    M hypervisor/arch/arm/gic-v3.c
    A hypervisor/arch/arm/include/asm/gic.h
    R hypervisor/arch/arm/include/asm/gic_common.h
    M hypervisor/arch/arm/irqchip.c
    M hypervisor/arch/arm/traps.c

  Log Message:
  -----------
  arm: Rename gic_common.h to gic.h

gic.h is already the only interface header for the GIC, so there is no
reason to add a suffix to it.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: eb06f3326053da7469cb6369e54b8029c558e782
      
https://github.com/siemens/jailhouse/commit/eb06f3326053da7469cb6369e54b8029c558e782
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M hypervisor/arch/arm/include/asm/gic.h
    M hypervisor/arch/arm/include/asm/platform.h

  Log Message:
  -----------
  arm: Include gic_v2/3.h from gic.h

Moving this include away from the platform.h prepares for getting rid of
latter.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 28d74817b7f69711a3d2453d2d625bbb5e928c82
      
https://github.com/siemens/jailhouse/commit/28d74817b7f69711a3d2453d2d625bbb5e928c82
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M hypervisor/arch/arm/include/asm/platform.h
    M hypervisor/arch/arm/smp-vexpress.c

  Log Message:
  -----------
  arm: Move SYSREGS_BASE into smp-vexpress module

It's a natural constant on this platform, and only there.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 9978638f93bf384da2c44cfd6e1597ea1fe5ac7d
      
https://github.com/siemens/jailhouse/commit/9978638f93bf384da2c44cfd6e1597ea1fe5ac7d
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M hypervisor/arch/arm/include/asm/gic_v2.h
    M hypervisor/arch/arm/include/asm/gic_v3.h
    M hypervisor/arch/arm/include/asm/platform.h

  Log Message:
  -----------
  arm: Move GIC size constants to gic_v2/3.h

These region mapping sizes are dictated by the spec rather than the
platform. GICV_SIZE was unused (it's always identical to GICC_SIZE).

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: f52974cd2e972a4a84370ef28279bd24f7a90540
      
https://github.com/siemens/jailhouse/commit/f52974cd2e972a4a84370ef28279bd24f7a90540
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M hypervisor/arch/arm/gic-common.c
    M hypervisor/arch/arm/gic-v2.c
    M hypervisor/arch/arm/gic-v3.c
    M hypervisor/arch/arm/irqchip.c

  Log Message:
  -----------
  arm: Remove gic*_size variables

They are true constants.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: ea00e192ca681dabb9cf14c0323d52f73a253a8e
      
https://github.com/siemens/jailhouse/commit/ea00e192ca681dabb9cf14c0323d52f73a253a8e
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M configs/Makefile
    M configs/apic-demo.c
    M configs/bananapi-gic-demo.c
    M configs/bananapi-uart-demo.c
    M configs/bananapi.c
    M configs/e1000-demo.c
    M configs/f2a88xm-hd3.c
    M configs/h87i.c
    M configs/imb-a180.c
    M configs/ioapic-demo.c
    M configs/ivshmem-demo.c
    M configs/jetson-tk1-demo.c
    M configs/jetson-tk1.c
    M configs/linux-x86-demo.c
    M configs/pci-demo.c
    M configs/qemu-vm.c
    M configs/smp-demo.c
    M configs/tiny-demo.c
    M configs/vexpress-gic-demo.c
    M configs/vexpress-linux-demo.c
    M configs/vexpress-uart-demo.c
    M configs/vexpress.c
    M tools/root-cell-config.c.tmpl

  Log Message:
  -----------
  configs: Enable evaluation of config.h

This enables the evaluation of config.h which will simplify switching
between GICv2 and v3 for the vexpress config. For that, we need to
switch the provider of types.h from Linux to Jailhouse.

Note that this change will require adjustment/recreation of local config
source files.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: e7a677cbaefce5d9595e8fd03aac930999d6119d
      
https://github.com/siemens/jailhouse/commit/e7a677cbaefce5d9595e8fd03aac930999d6119d
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M configs/bananapi.c
    M configs/jetson-tk1.c
    M configs/vexpress.c
    M hypervisor/arch/arm/control.c
    M hypervisor/arch/arm/dbg-write.c
    M hypervisor/arch/arm/gic-common.c
    M hypervisor/arch/arm/gic-v2.c
    M hypervisor/arch/arm/gic-v3.c
    R hypervisor/arch/arm/include/asm/platform.h
    M hypervisor/arch/arm/irqchip.c
    M hypervisor/arch/arm/traps.c
    M hypervisor/include/jailhouse/cell-config.h

  Log Message:
  -----------
  arm, configs: Move content of platform.h into system configuration

Overcome the constantly growing ugly platform.h by defining
platform_info.arm in the system configuration. We need the base
addresses of GICD/C/H/V/R here and the maintenance interrupt number. No
need to account for the fact that only GICv3 needs GICR and not C/H/V -
makes the definition more compact, and we have enough space.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 7e08f40f720c194691e00f244e9551b2064e1c69
      
https://github.com/siemens/jailhouse/commit/7e08f40f720c194691e00f244e9551b2064e1c69
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-09-25 (Sun, 25 Sep 2016)

  Changed paths:
    M hypervisor/arch/arm/gic-common.c
    M hypervisor/arch/arm/gic-v2.c
    M hypervisor/arch/arm/gic-v3.c
    M hypervisor/arch/arm/include/asm/gic.h

  Log Message:
  -----------
  arm: Move gicd_base declarations into header

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 5c2cc56accf4981b565adfeaf5dc86b66e6f5510
      
https://github.com/siemens/jailhouse/commit/5c2cc56accf4981b565adfeaf5dc86b66e6f5510
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/gic-v3.c

  Log Message:
  -----------
  arm: Cleanups in GICv3 version of gic_cpu_init

Make size expression more compact and do not compare pointer against 0.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 8215a1fef879c38433c9da4e22c618a622a90664
      
https://github.com/siemens/jailhouse/commit/8215a1fef879c38433c9da4e22c618a622a90664
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/gic-v3.c
    M hypervisor/arch/arm/include/asm/percpu.h

  Log Message:
  -----------
  arm: Make GICR matching in gic_handle_redist_access more readable

The various address calculations didn't help to understand the
underlying logic of the address match. Rework this by deriving an offset
into the GICR regions from the per-cpu physical addresses.

This will also enable moving the GICR hypervisor mapping away from 1:1.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 1202759790014e0a459be65a0a91e001d7b1d1b5
      
https://github.com/siemens/jailhouse/commit/1202759790014e0a459be65a0a91e001d7b1d1b5
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/gic-v2.c
    M hypervisor/arch/arm/gic-v3.c
    M hypervisor/arch/arm/irqchip.c

  Log Message:
  -----------
  arm: Prepare GIC for non-identity mapping

Read the physical GIC addresses from platform_info instead of relying on
the mapping addresses. This allows to map the resources at different
virtual addresses into the hypervisor address space.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: a1bb0022656890cfb4fad04623d94e8dc02bebab
      
https://github.com/siemens/jailhouse/commit/a1bb0022656890cfb4fad04623d94e8dc02bebab
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/include/jailhouse/paging.h
    M hypervisor/paging.c

  Log Message:
  -----------
  core: Introduce paging_map/unmap_device

These services are wrapping the common pattern of page allocation from
the remapping pool and then mapping of a physical device into the
hypervisor address space / the reverse of it. They will also replace the
ARM-specific Implementations.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: acf009bec9fada04458e248974a65fe44680338f
      
https://github.com/siemens/jailhouse/commit/acf009bec9fada04458e248974a65fe44680338f
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/pci.c

  Log Message:
  -----------
  core: Use paging_map/unmap_device in PCI layer

Less boilerplate code.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: d96ca77cc5a5e61f19a127d54857e9b9f832ec50
      
https://github.com/siemens/jailhouse/commit/d96ca77cc5a5e61f19a127d54857e9b9f832ec50
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/x86/amd_iommu.c
    M hypervisor/arch/x86/apic.c
    M hypervisor/arch/x86/ioapic.c

  Log Message:
  -----------
  x86: Use paging_map/unmap_device for AMD IOMMU, APIC and IOAPIC

We cannot use the functions for svm because it reuses the virtual
address for the AVIC page on all CPUs. And vtd maps all DMAR units
back-to-back, even when their physical addresses are scattered.

Still quite some boilerplate code removed.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 922781261a937a6d8d025f0cf87cb7f13aaa4c0b
      
https://github.com/siemens/jailhouse/commit/922781261a937a6d8d025f0cf87cb7f13aaa4c0b
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/gic-v2.c
    M hypervisor/arch/arm/gic-v3.c
    M hypervisor/arch/arm/irqchip.c
    M hypervisor/arch/arm/smp-vexpress.c

  Log Message:
  -----------
  arm: Use paging_map/unmap_device for GIC and vexpress sysregs

Less boilerplate code, arch_map/unmap_device becomes unused, and we also
properly allocate the virtual addresses of the mapped resources from the
remapping pool, instead of relying on identity mapping creating no
conflicts.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 57c4e8e5e9fddeec23ff52a99f930ae5f94753d1
      
https://github.com/siemens/jailhouse/commit/57c4e8e5e9fddeec23ff52a99f930ae5f94753d1
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/include/asm/setup.h
    M hypervisor/arch/arm/mmu_hyp.c

  Log Message:
  -----------
  arm: Remove unused arch_map/unmap_device

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 4763fe41cbd7ade0f8ee78281d03e291cab011a7
      
https://github.com/siemens/jailhouse/commit/4763fe41cbd7ade0f8ee78281d03e291cab011a7
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/include/asm/traps.h
    M hypervisor/arch/arm/mmio.c

  Log Message:
  -----------
  arm: Clean up includes of asm/traps.h

jailhouse/printk.h and asm/percpu.h belong to the module that lack it
as explicit inclusion.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 1bb122f5e2c4851f8d7cefc895510c14d9b65326
      
https://github.com/siemens/jailhouse/commit/1bb122f5e2c4851f8d7cefc895510c14d9b65326
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/caches.S
    M hypervisor/arch/arm/entry.S
    M hypervisor/arch/arm/exception.S
    R hypervisor/arch/arm/include/asm/head.h
    M hypervisor/arch/arm/include/asm/setup.h
    M hypervisor/arch/arm/include/asm/sysregs.h
    M hypervisor/arch/arm/include/asm/traps.h

  Log Message:
  -----------
  arm: Get rid of asm/head.h

Activate virt extension via sysregs.h, because only C modules the use
the sysreg macros will actually need that tweak. On the assembly side,
its much simpler to activate the extension explicitly. This allows us to
remove asm/head.h completely.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 9dc1e10a346e9d90bbf6566e208046c32132b914
      
https://github.com/siemens/jailhouse/commit/9dc1e10a346e9d90bbf6566e208046c32132b914
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/control.c
    M hypervisor/arch/arm/include/asm/setup.h
    M hypervisor/arch/arm/lib.c
    M hypervisor/arch/arm/setup.c

  Log Message:
  -----------
  arm: Remove some unneeded includes

Those are either not used or basic includes that come in implicitly.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: d3d2bc033b1f88da7840bb53e8a50d493499c381
      
https://github.com/siemens/jailhouse/commit/d3d2bc033b1f88da7840bb53e8a50d493499c381
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/control.c
    M hypervisor/arch/arm/include/asm/percpu.h

  Log Message:
  -----------
  arm: Push asm/psci.h to user site

percpu.h has no direct need for it.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 02d8367908e05860e49d5860b71e36ba389f1cb8
      
https://github.com/siemens/jailhouse/commit/02d8367908e05860e49d5860b71e36ba389f1cb8
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M inmates/lib/arm/gic-v3.c
    M inmates/lib/arm/include/gic.h

  Log Message:
  -----------
  inmates: arm: Fix GICv3 enabling

Found by Coverity: Make sure we only process SGIs, PPIs and SPIs.
Furthermore, we have to select the GICD_ISENABLER register for SPIs
based on the interrupt number first and then write the correct bit
between 0 and 31.

Fixes: 9ee8e1418938 ("arm: basic inmates demos")

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: be07319566620604afac2856ed651ab9fbff5f0e
      
https://github.com/siemens/jailhouse/commit/be07319566620604afac2856ed651ab9fbff5f0e
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/gic-v2.c

  Log Message:
  -----------
  arm: Fix gic_adjust_irq_target for GICv2

We need to shift by 8 bits, the width of the IRQ target field.

Fixes: 011ab917a150 ("arm: Rework interrupt affinity management on cell
creation")

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 6b1ba6dec7524be52e68c4cd35f6c6a1b2a68e01
      
https://github.com/siemens/jailhouse/commit/6b1ba6dec7524be52e68c4cd35f6c6a1b2a68e01
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/control.c
    M hypervisor/arch/arm/include/asm/irqchip.h
    M hypervisor/arch/arm/irqchip.c

  Log Message:
  -----------
  arm: Adjust irqchips only on arch_config_commit

Doing this earlier, during arch_cell_create, does not work because the
CPUs have not yet been assigned to their new owner at this point. Should
have noticed earlier: this aligns ARM with x86.

Fixes: 011ab917a150 ("arm: Rework interrupt affinity management on cell
creation")

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: bbf7a8757f12dafaeae85815151c47097f890ab4
      
https://github.com/siemens/jailhouse/commit/bbf7a8757f12dafaeae85815151c47097f890ab4
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-02 (Sun, 02 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/gic-common.c

  Log Message:
  -----------
  arm: Fix handle_irq_target for write accesses

This was broken since day #1: We didn't read the proper itargetsr, but
rather from some totally wrong offset in the GICD. Later patches didn't
get this as well and were only changing the offset into the GICD, not
fixing it.

Rework the routine by introducing irq_base, the first IRQ number that
shares the GICD_ITARGETSRn with the target IRQ.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: dd581430938eaf1b30a427be519f9fac51783be6
      
https://github.com/siemens/jailhouse/commit/dd581430938eaf1b30a427be519f9fac51783be6
  Author: Jan Kiszka <jan.kis...@siemens.com>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M hypervisor/arch/arm/include/asm/paging.h

  Log Message:
  -----------
  arm: Add barriers to arch_paging_flush_page_tlbs

This adds the barriers needed according to ARM DDI 0406C.c, D7.5.3. As
we only map MMIO and non-executable RAM, there is no need for BPIALLIS
in our case.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


  Commit: 7de8a700f35e45447a0ab25c627060d3fed8c097
      
https://github.com/siemens/jailhouse/commit/7de8a700f35e45447a0ab25c627060d3fed8c097
  Author: Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>
  Date:   2016-10-04 (Tue, 04 Oct 2016)

  Changed paths:
    M configs/jetson-tk1.c

  Log Message:
  -----------
  config: fix address overlap in TK1 configs

configs/jetson-tk1.c comments that the system should be started with
mem=1984' as cmdline option.  This reserves uppermost 64MiB of memory.
Hypervisor memory started at 0xfc000000 and reserved all of that memory,
so actually there has never been enough inmate RAM for jetson-tk1-demo.c.

Physical memory of the jetson-tk1-demo.c inmate started at 0xfbfe0000,
which overlaps with root cell memory. This is a configuration bug. As
soon as the root cell touches that part of the memory, jailhouse will
crash.

As a solution, simply spend more memory for jailhouse and its inmates.
Reserve 64MiB for inmates and 63MiB for the hypervisor.

Current RAM Layout of the TK1:
80000000-f7ffffff : root cell memory (1920MiB)
f8000000-fbffffff : available for inmates (64MiB)
fc000000-ffefffff : jailhouse hypervisor (63MiB)
fff00000-ffffffff : PSCI (1MiB)

Signed-off-by: Ralf Ramsauer <ralf.ramsa...@oth-regensburg.de>
Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>


Compare: 
https://github.com/siemens/jailhouse/compare/b267f36bfd95...7de8a700f35e

-- 
You received this message because you are subscribed to the Google Groups 
"Jailhouse" group.
To unsubscribe from this group and stop receiving emails from it, send an email 
to jailhouse-dev+unsubscr...@googlegroups.com.
For more options, visit https://groups.google.com/d/optout.

Reply via email to