The arm_dcaches_flush function is needed early on during initialization,
in order to flush the early bootstrap page tables for they hypervisor.

Based on patch by Antonios Motakis.

Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>
---
 hypervisor/arch/arm64/asm-defines.c |  6 +++++
 hypervisor/arch/arm64/caches.S      | 51 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/hypervisor/arch/arm64/asm-defines.c 
b/hypervisor/arch/arm64/asm-defines.c
index c026a3c..7db0bbb 100644
--- a/hypervisor/arch/arm64/asm-defines.c
+++ b/hypervisor/arch/arm64/asm-defines.c
@@ -2,18 +2,24 @@
  * Jailhouse AArch64 support
  *
  * Copyright (C) 2015 Huawei Technologies Duesseldorf GmbH
+ * Copyright (c) Siemens AG, 2016
  *
  * Authors:
  *  Antonios Motakis <antonios.mota...@huawei.com>
+ *  Jan Kiszka <jan.kis...@siemens.com>
  *
  * This work is licensed under the terms of the GNU GPL, version 2.  See
  * the COPYING file in the top-level directory.
  */
 
+#include <jailhouse/paging.h>
 #include <jailhouse/gen-defines.h>
 
 void common(void);
 
 void common(void)
 {
+       DEFINE(DCACHE_CLEAN_ASM, DCACHE_CLEAN);
+       DEFINE(DCACHE_INVALIDATE_ASM, DCACHE_INVALIDATE);
+       DEFINE(DCACHE_CLEAN_AND_INVALIDATE_ASM, DCACHE_CLEAN_AND_INVALIDATE);
 }
diff --git a/hypervisor/arch/arm64/caches.S b/hypervisor/arch/arm64/caches.S
index 400b4e6..39dad4a 100644
--- a/hypervisor/arch/arm64/caches.S
+++ b/hypervisor/arch/arm64/caches.S
@@ -2,15 +2,64 @@
  * Jailhouse AArch64 support
  *
  * Copyright (C) 2016 Huawei Technologies Duesseldorf GmbH
+ * Copyright (c) 2016 Siemens AG
  *
  * Authors:
  *  Antonios Motakis <antonios.mota...@huawei.com>
+ *  Jan Kiszka <jan.kis...@siemens.com>
  *
  * This work is licensed under the terms of the GNU GPL, version 2.  See
  * the COPYING file in the top-level directory.
  *
+ * Implementation derived from Linux source files:
+ *   - arch/arm64/mm/cache.S
+ *   - arch/arm64/mm/proc-macros.S
  */
 
+#include <asm/asm-defines.h>
+
+/*
+ * dcache_line_size - get the minimum D-cache line size from the CTR register.
+ */
+       .macro  dcache_line_size, reg, tmp
+       mrs     \tmp, ctr_el0                   // read CTR
+       ubfm    \tmp, \tmp, #16, #19            // cache line size encoding
+       mov     \reg, #4                        // bytes per word
+       lsl     \reg, \reg, \tmp                // actual cache line size
+       .endm
+
+/*
+ *     arm_dcaches_flush(addr, size, flush)
+ *
+ *     Ensure that the data held in the page addr is written back to the
+ *     page in question.
+ *
+ *     - addr    - address
+ *     - size    - size in question
+ *     - flush   - type of flush (see enum dcache_flush)
+ */
        .global arm_dcaches_flush
 arm_dcaches_flush:
-       b       .
+       dcache_line_size x3, x4
+       add     x1, x0, x1
+       sub     x4, x3, #1
+       bic     x0, x0, x4
+
+1:     cmp     x2, #DCACHE_CLEAN_ASM
+       b.ne    2f
+       dc      cvac, x0
+       b       4f
+
+2:     cmp     x2, #DCACHE_INVALIDATE_ASM
+       b.ne    3f
+       dc      ivac, x0
+       b       4f
+
+3:     dc      civac, x0                       // DCACHE_CLEAN_AND_INVALIDATE
+
+4:     add     x0, x0, x3
+       cmp     x0, x1
+       b.lo    1b
+
+       dsb     sy
+       ret
-- 
2.1.4

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