Branch: refs/heads/wip/arm-ivshmem
Home: https://github.com/siemens/jailhouse
Commit: 40ff11bef644f1180d45bb22b42fae65b3ad1950
https://github.com/siemens/jailhouse/commit/40ff11bef644f1180d45bb22b42fae65b3ad1950
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/arch/x86/vtd.c
A hypervisor/include/jailhouse/ivshmem.h
M hypervisor/include/jailhouse/pci.h
M hypervisor/pci.c
M hypervisor/pci_ivshmem.c
Log Message:
-----------
core: ivshmem: Introduce separate header file
Stop piggybacking with PCI for ivshmem-specific prototypes. This will
help making non-x86 support for ivshmem cleaner.
We already move the struct pci_ivshmem_endpoint into the header because
the arch-specific code will need it.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 1e22338f0895620e66e7992c423982122473851a
https://github.com/siemens/jailhouse/commit/1e22338f0895620e66e7992c423982122473851a
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/arch/x86/Kbuild
M hypervisor/arch/x86/vtd.c
M hypervisor/include/jailhouse/ivshmem.h
M hypervisor/include/jailhouse/pci.h
A hypervisor/ivshmem.c
M hypervisor/pci.c
R hypervisor/pci_ivshmem.c
Log Message:
-----------
core: ivshmem: Remove "pci" tagging from function and module names
The ivshmem device is PCI-only, and it seems it will remain like that,
even when expanding to targets without physical PCI support. Therefore,
it adds no value to have "pci_" in its names all over the place because
the will be no PCI-free variant in parallel.
Besides the renaming, this also consolidates pci_ivshmem_update_msix and
ivshmem_update_msix into a single service.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: c79ce1e53f24a0eaead73979fb827f7f5070b27d
https://github.com/siemens/jailhouse/commit/c79ce1e53f24a0eaead73979fb827f7f5070b27d
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/arch/x86/include/asm/apic.h
M hypervisor/arch/x86/include/asm/pci.h
M hypervisor/arch/x86/pci.c
M hypervisor/ivshmem.c
Log Message:
-----------
x86: pci: Rename pci_translate_msi_vector and move prototype to asm/pci.h
The name should reflect that this is an x86-only function. And it is a
PCI service, implemented in x86/pci.c. Thus the prototype rather belongs
into asm/pci.h.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 7aad4176ba6b26ed5ba29a11c0654ade6bdc5131
https://github.com/siemens/jailhouse/commit/7aad4176ba6b26ed5ba29a11c0654ade6bdc5131
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/arch/x86/Kbuild
A hypervisor/arch/x86/include/asm/ivshmem.h
A hypervisor/arch/x86/ivshmem.c
M hypervisor/arch/x86/vtd.c
M hypervisor/include/jailhouse/ivshmem.h
M hypervisor/ivshmem.c
M hypervisor/pci.c
Log Message:
-----------
core: ivhsmem: Factor out architecture-specific parts
So far the ivshmem code assumed to run only on x86. In order to prepare
it for reuse on other architectures (ARM, ARM64), factor out the bits
and pieces that are arch-specific and implement them for x86.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 384be3fcbf2a5acbbfb589ab144fc784d3343452
https://github.com/siemens/jailhouse/commit/384be3fcbf2a5acbbfb589ab144fc784d3343452
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/pci.c
Log Message:
-----------
core: pci: Add byte and word access support for mmconfig
Supporting more accesses sizes actually makes the case slightly simpler,
thanks to mmio_perform_access. Moreover, this will help introducing PCI
support on ARM where accesses of less than 4 bytes take place.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: a8d197b7ea70f7f73c572bc4a4136deac7b67344
https://github.com/siemens/jailhouse/commit/a8d197b7ea70f7f73c572bc4a4136deac7b67344
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M configs/f2a88xm-hd3.c
M configs/h87i.c
M configs/imb-a180.c
M configs/qemu-vm.c
M hypervisor/include/jailhouse/cell-config.h
M hypervisor/pci.c
M tools/root-cell-config.c.tmpl
Log Message:
-----------
core, configs, tools: Make mmconfig PCI platform parameters generic
We will reuse them non-x86 architectures.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 2be13974d3b4cbc76ca39168edb0342ef16815cc
https://github.com/siemens/jailhouse/commit/2be13974d3b4cbc76ca39168edb0342ef16815cc
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/arch/arm/Kbuild
A hypervisor/arch/arm/lib.c
Log Message:
-----------
arm: Provide __aeabi_llsl and __aeabi_llsr
Will be required by the PCI layer. It's not worth optimizing this in
assembly, the compiler is already pretty good in this.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 3f673e284c77c51c639536055829fafae9e1210d
https://github.com/siemens/jailhouse/commit/3f673e284c77c51c639536055829fafae9e1210d
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/Makefile
M hypervisor/arch/arm-common/Kbuild
A hypervisor/arch/arm-common/include/asm/ivshmem.h
A hypervisor/arch/arm-common/ivshmem.c
A hypervisor/arch/arm-common/pci.c
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/mmio.c
M hypervisor/arch/arm64/include/asm/paging.h
M hypervisor/arch/x86/Kbuild
Log Message:
-----------
arm, arm64: Prepare for PCI support
This adds the required stubs and functions of physical PCI support on
ARM and ARM64. It also switches to building the generic PCI and ivshmem
modules unconditionally for all archs. Mapping the MMCONFIG space will
require a larger remapping region, so this is extended on both ARM and
ARM64.
This does not yet initialize PCI for the new archs, though. Moreover,
ivshmem interrupt delivery is not yet implemented.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 09720a36a7550c07fc0f903549fbfb9163d807f0
https://github.com/siemens/jailhouse/commit/09720a36a7550c07fc0f903549fbfb9163d807f0
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/control.c
Log Message:
-----------
core: Rename shutdown to hypervisor_disable
We will use "shutdown" for encapsulating arch_shutdown + generic steps.
No functional changes.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 11fc19386e76da9df8100f9eb873e10e3462c724
https://github.com/siemens/jailhouse/commit/11fc19386e76da9df8100f9eb873e10e3462c724
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/arch/x86/control.c
M hypervisor/arch/x86/mmio.c
M hypervisor/arch/x86/setup.c
M hypervisor/control.c
M hypervisor/include/jailhouse/control.h
M hypervisor/mmio.c
M hypervisor/setup.c
Log Message:
-----------
core: Make PCI a generic feature
Move PCI initialization functions from x86 into the core, effectively
enabling it for all architectures.
PCI is now initialized last, both during common setup as well as on cell
creation. This means an ordering change for x86, but that is without
side effects.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: c0ff2e60584e7dd730bd48cda79ce1a9acdc202e
https://github.com/siemens/jailhouse/commit/c0ff2e60584e7dd730bd48cda79ce1a9acdc202e
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/pci.c
Log Message:
-----------
core: pci: Permit write access to read-only Header Type register
On ARM, Linux will update BIST, Latency Timer and Cache Line Size in a
single 32-bit write, which includes the Header Type register. This traps
so far. But Header Type is specified to be read-only, thus writes have
no effect and can safely be allowed as well.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 91746eb3a26a691955e6d8a9a8131f4df0f3152e
https://github.com/siemens/jailhouse/commit/91746eb3a26a691955e6d8a9a8131f4df0f3152e
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/arch/arm-common/gic-common.c
M hypervisor/arch/arm-common/include/asm/gic.h
M hypervisor/arch/arm-common/irqchip.c
Log Message:
-----------
arm-common: Add support for interrupt injection via GICD
This will be useful for injecting interrupts on behalf of virtual
devices, namely ivshmem. It allows to let the hardware do the routing to
the target CPU, instead of implementing this in software.
Reuse the existing irqchip_set_pending interface for this, defining
GICD-based injection being requested if a NULL target CPU is passed.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: d5e391800316cea58068671bf8be68b59b3e06b5
https://github.com/siemens/jailhouse/commit/d5e391800316cea58068671bf8be68b59b3e06b5
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/arch/arm-common/include/asm/ivshmem.h
M hypervisor/arch/arm-common/ivshmem.c
Log Message:
-----------
arm-common: Add MSI-X support for ivshmem devices based on GICv2m
If system comes with a GICv2m, we can piggyback with it to emulate MSI-X
vector support of ivshmem. GICv2m means that the MSI data field contains
the target interrupt number, to be injected into the GICD. We validate
and cache the value on arch_ivshmem_update_msix and simply inject it via
the physical GICD on arch_ivshmem_write_doorbell.
Yet missing is validation of the MSI address field. Also, we do not have
any of the GICv2m quirk workaround implemented that Linux carries
because our reference system, AMD Seattle, is implemented according to
the Server Base System Architecture spec.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 6d78eb022e7ef20bac2bedd98df02aa4c7f90cec
https://github.com/siemens/jailhouse/commit/6d78eb022e7ef20bac2bedd98df02aa4c7f90cec
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/include/jailhouse/cell-config.h
M hypervisor/pci.c
Log Message:
-----------
core: pci: Add virtual host controller
Yes, it is that simple: For targets without physical PCI support, we can
simply expose an mmconfig region in order to provide ivshmem devices to
the guests. All we need to do is to register the configured MMIO region
but skip the mapping of the region physically. A new flag in the system
config controls this.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 80305af737c27480aabe69bfdaafe7b511f86448
https://github.com/siemens/jailhouse/commit/80305af737c27480aabe69bfdaafe7b511f86448
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/include/jailhouse/cell-config.h
M tools/jailhouse-cell-linux
Log Message:
-----------
core, tools: Add IRQ base number for virtual PCI hosts to cell config
In order to inject interrupts from virtual devices, we need to know the
(virtual) mapping of the VPCI host controller interrupts on the system
interrupt space. Introduce a per-cell config field that encodes this
base. It will only be used on targets without (suitable) physical MSI
support, which excludes x86.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: f7461412cc74f8bf7144c4ffe387b40f4f92504b
https://github.com/siemens/jailhouse/commit/f7461412cc74f8bf7144c4ffe387b40f4f92504b
Author: Jan Kiszka <[email protected]>
Date: 2016-11-19 (Sat, 19 Nov 2016)
Changed paths:
M hypervisor/arch/arm-common/ivshmem.c
M hypervisor/arch/x86/ivshmem.c
M hypervisor/include/jailhouse/ivshmem.h
M hypervisor/ivshmem.c
Log Message:
-----------
core: ivshmem: Introduce arch_ivshmem_init
Called at the end of the endpoint device setup, will be needed for
initialization INTx emulation.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 6410125d54405c9473e61002a42479f704e28532
https://github.com/siemens/jailhouse/commit/6410125d54405c9473e61002a42479f704e28532
Author: Jan Kiszka <[email protected]>
Date: 2016-11-21 (Mon, 21 Nov 2016)
Changed paths:
M hypervisor/arch/arm-common/ivshmem.c
M hypervisor/ivshmem.c
Log Message:
-----------
arm: ivshmem: Add support for INTx-based interrupt injection
Fall back to INTx in case an ivshmem device comes without MSI-X vectors.
This is now implemented for ARM, using standard PCI pin rotation based
on the device slot.
x86 has no need for INTx as MSI-X is always supported (plus there is a
less uniform legacy INTx injection path which prevents a generic
solution).
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 79ea342eead65354d7865aee2f2be1466b80ad7c
https://github.com/siemens/jailhouse/commit/79ea342eead65354d7865aee2f2be1466b80ad7c
Author: Jan Kiszka <[email protected]>
Date: 2016-11-21 (Mon, 21 Nov 2016)
Changed paths:
M driver/cell.c
M driver/main.c
M driver/pci.c
M driver/pci.h
Log Message:
-----------
driver: Remove shared memory devices prior to disabling the hypervisor
Once the Jailhouse is disabled, there is no one handling accesses to the
virtual shared memory devices anymore. So better remove them from Linux
before the actual disabling hypercall. To remain symmetric, we also pull
adding out of jailhouse_cell_register_root.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 550e95a8466c4488f18ae4900f229a029189d7e2
https://github.com/siemens/jailhouse/commit/550e95a8466c4488f18ae4900f229a029189d7e2
Author: Jan Kiszka <[email protected]>
Date: 2016-11-21 (Mon, 21 Nov 2016)
Changed paths:
M driver/Makefile
M driver/main.c
M driver/pci.c
M driver/pci.h
A driver/vpci_template.dts
Log Message:
-----------
driver: Register virtual PCI controller via device tree overlay
Commit: 456cd57d39755332666119e62819a55c1b31b3f7
https://github.com/siemens/jailhouse/commit/456cd57d39755332666119e62819a55c1b31b3f7
Author: Jan Kiszka <[email protected]>
Date: 2016-11-21 (Mon, 21 Nov 2016)
Changed paths:
M configs/amd-seattle-linux-demo.c
M configs/amd-seattle.c
M configs/dts/inmate-amd-seattle.dts
Log Message:
-----------
config: Enable PCI and inter-cell communication for AMD Seattle
Describe the PCI resources of the AMD Seattle so that devices can be
reassigned.
Also add one ivshmem device for networking purposes and extend the
non-root Linux cell accordingly. We can safely expose the physical
GICv2m for this purpose, but read-only. To avoid that root and non-root
cell use the same MSI frame (which are reported by the GICv2m),
overwrite the frame parameter in the non-root cell device tree.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 7ffe47e22a6a8f619b3d2e1bb38b535735e17b07
https://github.com/siemens/jailhouse/commit/7ffe47e22a6a8f619b3d2e1bb38b535735e17b07
Author: Jan Kiszka <[email protected]>
Date: 2016-11-21 (Mon, 21 Nov 2016)
Changed paths:
M configs/dts/inmate-jetson-tk1.dts
M configs/jetson-tk1-linux-demo.c
M configs/jetson-tk1.c
Log Message:
-----------
configs: Enable inter-cell communication for Jetson TK1
Commit: 254016c56c1cf962d30d4d3492ac5102b8e933c0
https://github.com/siemens/jailhouse/commit/254016c56c1cf962d30d4d3492ac5102b8e933c0
Author: Jan Kiszka <[email protected]>
Date: 2016-11-21 (Mon, 21 Nov 2016)
Changed paths:
M configs/bananapi-linux-demo.c
M configs/bananapi.c
M configs/dts/inmate-bananapi.dts
Log Message:
-----------
configs: Enable inter-cell communication for Banana Pi
Commit: 6ff6cd97cbb0bed7404825098d6bb15b31d60a64
https://github.com/siemens/jailhouse/commit/6ff6cd97cbb0bed7404825098d6bb15b31d60a64
Author: Jan Kiszka <[email protected]>
Date: 2016-11-21 (Mon, 21 Nov 2016)
Changed paths:
M configs/dts/inmate-hikey.dts
M configs/hikey-linux-demo.c
M configs/hikey.c
Log Message:
-----------
configs: Enable inter-cell communication for HiKey
Compare:
https://github.com/siemens/jailhouse/compare/f1a28db02173...6ff6cd97cbb0
--
You received this message because you are subscribed to the Google Groups
"Jailhouse" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to [email protected].
For more options, visit https://groups.google.com/d/optout.
