Branch: refs/heads/next
Home: https://github.com/siemens/jailhouse
Commit: 891240c9c868cf75bca454b858f6d237cee82212
https://github.com/siemens/jailhouse/commit/891240c9c868cf75bca454b858f6d237cee82212
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/arch/x86/vtd.c
A hypervisor/include/jailhouse/ivshmem.h
M hypervisor/include/jailhouse/pci.h
M hypervisor/pci.c
M hypervisor/pci_ivshmem.c
Log Message:
-----------
core: ivshmem: Introduce separate header file
Stop piggybacking with PCI for ivshmem-specific prototypes. This will
help making non-x86 support for ivshmem cleaner.
We already move the struct pci_ivshmem_endpoint into the header because
the arch-specific code will need it.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 7fe2e283f289ac7723859f1a866f01a1c4af5c9a
https://github.com/siemens/jailhouse/commit/7fe2e283f289ac7723859f1a866f01a1c4af5c9a
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/arch/x86/Kbuild
M hypervisor/arch/x86/vtd.c
M hypervisor/include/jailhouse/ivshmem.h
M hypervisor/include/jailhouse/pci.h
A hypervisor/ivshmem.c
M hypervisor/pci.c
R hypervisor/pci_ivshmem.c
Log Message:
-----------
core: ivshmem: Remove "pci" tagging from function and module names
The ivshmem device is PCI-only, and it seems it will remain like that,
even when expanding to targets without physical PCI support. Therefore,
it adds no value to have "pci_" in its names all over the place because
the will be no PCI-free variant in parallel.
Besides the renaming, this also consolidates pci_ivshmem_update_msix and
ivshmem_update_msix into a single service.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 0b3588ebc7b28b2032fc4fa1d577ae77822b645d
https://github.com/siemens/jailhouse/commit/0b3588ebc7b28b2032fc4fa1d577ae77822b645d
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/arch/x86/include/asm/apic.h
M hypervisor/arch/x86/include/asm/pci.h
M hypervisor/arch/x86/pci.c
M hypervisor/ivshmem.c
Log Message:
-----------
x86: pci: Rename pci_translate_msi_vector and move prototype to asm/pci.h
The name should reflect that this is an x86-only function. And it is a
PCI service, implemented in x86/pci.c. Thus the prototype rather belongs
into asm/pci.h.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 8ab4007aac3917230232cc892ec39d2afa6469fc
https://github.com/siemens/jailhouse/commit/8ab4007aac3917230232cc892ec39d2afa6469fc
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/arch/x86/Kbuild
A hypervisor/arch/x86/include/asm/ivshmem.h
A hypervisor/arch/x86/ivshmem.c
M hypervisor/arch/x86/vtd.c
M hypervisor/include/jailhouse/ivshmem.h
M hypervisor/ivshmem.c
M hypervisor/pci.c
Log Message:
-----------
core: ivhsmem: Factor out architecture-specific parts
So far the ivshmem code assumed to run only on x86. In order to prepare
it for reuse on other architectures (ARM, ARM64), factor out the bits
and pieces that are arch-specific and implement them for x86.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: b14eb1d511f8abbbc2c366977a01427695aa27f5
https://github.com/siemens/jailhouse/commit/b14eb1d511f8abbbc2c366977a01427695aa27f5
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/pci.c
Log Message:
-----------
core: pci: Add byte and word access support for mmconfig
Supporting more accesses sizes actually makes the case slightly simpler,
thanks to mmio_perform_access. Moreover, this will help introducing PCI
support on ARM where accesses of less than 4 bytes take place.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 938f9eef58e2ae40b19965008d4ea682dacf0732
https://github.com/siemens/jailhouse/commit/938f9eef58e2ae40b19965008d4ea682dacf0732
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M configs/f2a88xm-hd3.c
M configs/h87i.c
M configs/imb-a180.c
M configs/qemu-vm.c
M hypervisor/include/jailhouse/cell-config.h
M hypervisor/pci.c
M tools/root-cell-config.c.tmpl
Log Message:
-----------
core, configs, tools: Make mmconfig PCI platform parameters generic
We will reuse them non-x86 architectures.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: a157335792cf55bbc898b9b4be49cd3c74a12b4c
https://github.com/siemens/jailhouse/commit/a157335792cf55bbc898b9b4be49cd3c74a12b4c
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/arch/arm/Kbuild
A hypervisor/arch/arm/lib.c
Log Message:
-----------
arm: Provide __aeabi_llsl and __aeabi_llsr
Will be required by the PCI layer. It's not worth optimizing this in
assembly, the compiler is already pretty good in this.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 815f522b286fa8b9a361a593e88c14098c61a3dd
https://github.com/siemens/jailhouse/commit/815f522b286fa8b9a361a593e88c14098c61a3dd
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/Makefile
M hypervisor/arch/arm-common/Kbuild
A hypervisor/arch/arm-common/include/asm/ivshmem.h
A hypervisor/arch/arm-common/ivshmem.c
A hypervisor/arch/arm-common/pci.c
M hypervisor/arch/arm/include/asm/paging.h
M hypervisor/arch/arm/mmio.c
M hypervisor/arch/arm64/include/asm/paging.h
M hypervisor/arch/x86/Kbuild
Log Message:
-----------
arm, arm64: Prepare for PCI support
This adds the required stubs and functions of physical PCI support on
ARM and ARM64. It also switches to building the generic PCI and ivshmem
modules unconditionally for all archs. Mapping the MMCONFIG space will
require a larger remapping region, so this is extended on both ARM and
ARM64.
This does not yet initialize PCI for the new archs, though. Moreover,
ivshmem interrupt delivery is not yet implemented.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: c3510671959958225513a3c1e65547cbfee714e2
https://github.com/siemens/jailhouse/commit/c3510671959958225513a3c1e65547cbfee714e2
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/control.c
Log Message:
-----------
core: Rename shutdown to hypervisor_disable
We will use "shutdown" for encapsulating arch_shutdown + generic steps.
No functional changes.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 4eaa09112c15a40f75fe8085db9d8564f49e2ac5
https://github.com/siemens/jailhouse/commit/4eaa09112c15a40f75fe8085db9d8564f49e2ac5
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/arch/x86/control.c
M hypervisor/arch/x86/mmio.c
M hypervisor/arch/x86/setup.c
M hypervisor/control.c
M hypervisor/include/jailhouse/control.h
M hypervisor/mmio.c
M hypervisor/setup.c
Log Message:
-----------
core: Make PCI a generic feature
Move PCI initialization functions from x86 into the core, effectively
enabling it for all architectures.
PCI is now initialized last, both during common setup as well as on cell
creation. This means an ordering change for x86, but that is without
side effects.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 5bd44b9ae43927df99cbf32d1210ae330e556cc4
https://github.com/siemens/jailhouse/commit/5bd44b9ae43927df99cbf32d1210ae330e556cc4
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/pci.c
Log Message:
-----------
core: pci: Permit write access to read-only Header Type register
On ARM, Linux will update BIST, Latency Timer and Cache Line Size in a
single 32-bit write, which includes the Header Type register. This traps
so far. But Header Type is specified to be read-only, thus writes have
no effect and can safely be allowed as well.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: e2bf265db664b4f9d914f8034f0e8745d0857c02
https://github.com/siemens/jailhouse/commit/e2bf265db664b4f9d914f8034f0e8745d0857c02
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/arch/arm-common/gic-common.c
M hypervisor/arch/arm-common/include/asm/gic.h
M hypervisor/arch/arm-common/irqchip.c
Log Message:
-----------
arm-common: Add support for interrupt injection via GICD
This will be useful for injecting interrupts on behalf of virtual
devices, namely ivshmem. It allows to let the hardware do the routing to
the target CPU, instead of implementing this in software.
Reuse the existing irqchip_set_pending interface for this, defining
GICD-based injection being requested if a NULL target CPU is passed.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 893c9273eb5ee65b8ad2a9be37b7f8e40eea7b99
https://github.com/siemens/jailhouse/commit/893c9273eb5ee65b8ad2a9be37b7f8e40eea7b99
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/arch/arm-common/include/asm/ivshmem.h
M hypervisor/arch/arm-common/ivshmem.c
Log Message:
-----------
arm-common: Add MSI-X support for ivshmem devices based on GICv2m
If system comes with a GICv2m, we can piggyback with it to emulate MSI-X
vector support of ivshmem. GICv2m means that the MSI data field contains
the target interrupt number, to be injected into the GICD. We validate
and cache the value on arch_ivshmem_update_msix and simply inject it via
the physical GICD on arch_ivshmem_write_doorbell.
Yet missing is validation of the MSI address field. Also, we do not have
any of the GICv2m quirk workaround implemented that Linux carries
because our reference system, AMD Seattle, is implemented according to
the Server Base System Architecture spec.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 7b9f373dcfc14a4951928c43ded9c02b9f1ac02c
https://github.com/siemens/jailhouse/commit/7b9f373dcfc14a4951928c43ded9c02b9f1ac02c
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/include/jailhouse/cell-config.h
M hypervisor/pci.c
Log Message:
-----------
core: pci: Add virtual host controller
Yes, it is that simple: For targets without physical PCI support, we can
simply expose an mmconfig region in order to provide ivshmem devices to
the guests. All we need to do is to register the configured MMIO region
but skip the mapping of the region physically. A new flag in the system
config controls this.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 66a22a9cca2e215518f620f032d31a9723a02b67
https://github.com/siemens/jailhouse/commit/66a22a9cca2e215518f620f032d31a9723a02b67
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/include/jailhouse/cell-config.h
M tools/jailhouse-cell-linux
Log Message:
-----------
core, tools: Add IRQ base number for virtual PCI hosts to cell config
In order to inject interrupts from virtual devices, we need to know the
(virtual) mapping of the VPCI host controller interrupts on the system
interrupt space. Introduce a per-cell config field that encodes this
base. It will only be used on targets without (suitable) physical MSI
support, which excludes x86.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 7c810aae1913566ce05b476a9f2006b38fd28347
https://github.com/siemens/jailhouse/commit/7c810aae1913566ce05b476a9f2006b38fd28347
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/arch/arm-common/ivshmem.c
M hypervisor/arch/x86/ivshmem.c
M hypervisor/include/jailhouse/ivshmem.h
M hypervisor/ivshmem.c
Log Message:
-----------
core: ivshmem: Introduce arch_ivshmem_init
Called at the end of the endpoint device setup, will be needed for
initialization INTx emulation.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 0974b6e5796c05cb56f1941f105aab408e0382ce
https://github.com/siemens/jailhouse/commit/0974b6e5796c05cb56f1941f105aab408e0382ce
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M hypervisor/arch/arm-common/ivshmem.c
M hypervisor/ivshmem.c
Log Message:
-----------
arm: ivshmem: Add support for INTx-based interrupt injection
Fall back to INTx in case an ivshmem device comes without MSI-X vectors.
This is now implemented for ARM, using standard PCI pin rotation based
on the device slot.
x86 has no need for INTx as MSI-X is always supported (plus there is a
less uniform legacy INTx injection path which prevents a generic
solution).
Signed-off-by: Jan Kiszka <[email protected]>
Commit: ce6eb3cc0f2d5586f879379ac7b24fd391bf42a6
https://github.com/siemens/jailhouse/commit/ce6eb3cc0f2d5586f879379ac7b24fd391bf42a6
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M driver/cell.c
M driver/main.c
M driver/pci.c
M driver/pci.h
Log Message:
-----------
driver: Remove shared memory devices prior to disabling the hypervisor
Once the Jailhouse is disabled, there is no one handling accesses to the
virtual shared memory devices anymore. So better remove them from Linux
before the actual disabling hypercall. To remain symmetric, we also pull
adding out of jailhouse_cell_register_root.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 3eb0841fa4269e1024f204d485a416b2648b1072
https://github.com/siemens/jailhouse/commit/3eb0841fa4269e1024f204d485a416b2648b1072
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M driver/Makefile
M driver/main.c
M driver/pci.c
M driver/pci.h
A driver/vpci_template.dts
Log Message:
-----------
driver: Register virtual PCI controller via device tree overlay
In order to add a virtual PCI host controller to the root cell after
Jailhouse activation on ARM/ARM64, we need to inject a device tree
modification. For this purpose, overlays were invented and are already
support by upstream since 3.19.
All we need to do is to fill a fragment template with some variable
parameters that can be derived from the system configuration: virtual
IRQ base, ECAM base address, and the uncached memory window size, which
can be derived from the number of ivshmem devices. We also need to
resolve the link to the GIC as the host's device tree may not have the
required symbols included.
Once the fragment is patched, we can register it, and Linux will detect
and handle the new platform device.
Note that the upstream pci-host-generic Linux driver still has issues
when it comes to unloading (and actually also rollback on errors).
Fixing this is WiP.
To use this feature with the Tegra K1, the kernel has to be patched to
allow multi-domain PCI so that a second PCI host controller can be
enabled besides the non-extensible physical controller (see
https://groups.google.com/d/msg/jailhouse-dev/5BnCAFAzykI/wHgj2UUbCwAJ).
Signed-off-by: Jan Kiszka <[email protected]>
Commit: faba1be3b0d36497db95b44241dcec96bc2d8909
https://github.com/siemens/jailhouse/commit/faba1be3b0d36497db95b44241dcec96bc2d8909
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M configs/amd-seattle-linux-demo.c
M configs/amd-seattle.c
M configs/dts/inmate-amd-seattle.dts
Log Message:
-----------
config: Enable PCI and inter-cell communication for AMD Seattle
Describe the PCI resources of the AMD Seattle so that devices can be
reassigned.
Also add one ivshmem device for networking purposes and extend the
non-root Linux cell accordingly. We can safely expose the physical
GICv2m for this purpose, but read-only. To avoid that root and non-root
cell use the same MSI frame (which are reported by the GICv2m),
overwrite the frame parameter in the non-root cell device tree.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: fa26c0d861b7e8da9e78f89c8ccf4d9f843ca028
https://github.com/siemens/jailhouse/commit/fa26c0d861b7e8da9e78f89c8ccf4d9f843ca028
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M configs/dts/inmate-jetson-tk1.dts
M configs/jetson-tk1-linux-demo.c
M configs/jetson-tk1.c
Log Message:
-----------
configs: Enable inter-cell communication for Jetson TK1
Add ivshmem devices to root cell and linux-demo for networking purposes.
A virtual PCI host is introduced and INTx SPIs are carefully selected
for both sides so that they fall into the supported set of the GICD and
do not overlap with actually used interrupts.
The K1 only supports 160 SPIs, so adjust the root cell mask at this
chance as well.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 07a5ce205c961b738f988d914d5c8ea6dbc1750b
https://github.com/siemens/jailhouse/commit/07a5ce205c961b738f988d914d5c8ea6dbc1750b
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M configs/bananapi-linux-demo.c
M configs/bananapi.c
M configs/dts/inmate-bananapi.dts
Log Message:
-----------
configs: Enable inter-cell communication for Banana Pi
Add ivshmem devices to root cell and linux-demo for networking purposes.
A virtual PCI host is introduced and INTx SPIs are carefully selected
for both sides so that they fall into the supported set of the GICD and
do not overlap with actually used interrupts.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 5771651f598cfa4785027bfc77e7f91ee878c818
https://github.com/siemens/jailhouse/commit/5771651f598cfa4785027bfc77e7f91ee878c818
Author: Jan Kiszka <[email protected]>
Date: 2016-11-24 (Thu, 24 Nov 2016)
Changed paths:
M configs/dts/inmate-hikey.dts
M configs/hikey-linux-demo.c
M configs/hikey.c
Log Message:
-----------
configs: Enable inter-cell communication for HiKey
Add ivshmem devices to root cell and linux-demo for networking purposes.
A virtual PCI host is introduced and INTx SPIs are carefully selected
for both sides so that they fall into the supported set of the GICD and
do not overlap with actually used interrupts.
Signed-off-by: Jan Kiszka <[email protected]>
Compare:
https://github.com/siemens/jailhouse/compare/3599248e5291...5771651f598c
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