Hi Errico,
the timer interrupt 27 is a per-CPU-Interrupt, also known as Private
Peripheral Interrupt (PPI). So every CPU has its own GICC and therefore
its own timer. So no mapping is needed as it is already mapped per
definition. It is not described in the Tegra-X1 manual I guess because
it
is processor specific - not platform specific. So you will have to look
in the GIC specification for more information [1]. Which interrupt did
you try to route? Which system hangs, if you enable the interrupt? Is
it the whole system, just the non-root cell or just the root cell? If
the whole system hangs I guess there is a bug in the system
configuration or in jailhouse.
I guess the best way to explain how to configure a specific interrupt is
by an example. With pin_base you tell jailhouse where the interrupts start.
As the first 32 Interrupts are CPU specific you start with 32. In the
bitmap you have to add the required bits to set. If you want to set an
interrupt with a number higher than 160 you will have to add a second
irqchip with the pin_base 160. The following example shows how to
configure UARTA and UARTD on the Jetson-TK1. In which line to insert the
interrupt number is determined by definition of primary, secondary, ...
interrupt controller in the manual [1].
As the first 32 interrupt numbers are already reserved you should explicitly
add the 32 to your interrupt number. As the specified interrupt numbers are
determined by the lines you put them in you have to get the remainder between
0 and 31.
.irqchips = {
/* GIC */ {
.address = 0x50041000,
.pin_base = 32,
.pin_bitmap = {
0,
(1 << ((36 + 32) % 32)),
(1 << ((90 + 32) % 32)),
0,
},
},
},
As I never used the FreeRTOS Cell I can't help you with that questions.
[1]
http://www.cl.cam.ac.uk/research/srg/han/ACS-P35/zynq/arm_gic_architecture_specification.pdf
Best Regards
Andreas Kölbl
Am 22.02.2017 um 14:46 schrieb Errico Guidieri:
> Dear guys,
>
> I need to route a specific interrupt to my non-root cell (based on
> jetson-demo.cell) on a ARM64 device (TegraTX1), and I have the
> following questions.
>
> 1. I've seen in gic-demo that interrupt 27, that seems to be tied to
> ARMv8 CPU internal Timer, even thought this is not reporterd in
> TegraX1 RFM AFAICS, is available to the non-root cell even without
> providing any specific IRQ configuration in the non-root cell
> configuration (jetson-demo.c cell). However, if I try to enable a
> different IRQ, the system hangs (I would have expected an exception
> TBH). Is there any reason why the timer interrupt behaves differently
> than the others ?
>
> 2. How do I configure the non-root cell to route a specific IRQ to my
> cell I guess that I've to use the jailhouse_irqchip structure and the
> .irqchips field, providing the right address and bitmask. However, I
> can't figure out these values.
> I'm confused since I noted that in the FreeRTOS cell the GIC address
> differs between the root cell and the non-root cell, and I can't
> figure out the reason.
> Even the bitmask value is not clear since the bit set by the FreeRTOS
> cell is IRQNO - 32: is it this a constant requiremet for GIC? In other
> words in any implementation of ARM that use GIC am I supposed to
> subtract 32 from the number I find in the Hardware Reference Manual?
>
> 3. I also noted that the FreeRTOS porting has re-implemented the
> inmate library from scratch and it does not link against the usual
> Jailhouse library. Since their implementation provide basically the
> same services with a few small additions (e.g., priorities handling
> for IRQs), I wonder the reason why they have chosen to use a different
> implementation rather than merging these additions to the mainline
> project.
>
> 4. This question is more a curiosity. In header.S the irq vector
> entries do not save and restore the scratch/volatile registers. IMHO
> this seems to not match the ARMv8 ABI and could even bring to abnormal
> behavior in some circumstances. Is it correct or am I wrong ?
> original ARM porting (32 bit) used GCC
> __attribute__((interrupt("IRQ"))) for vector_irq function, but this
> strategy is no more available on ARM64 (I don't know why this features
> has not been added for ARMv8 version of the GCC too).
>
> Many thanks and best regards,
>
> Errico Guidieri
>
> --
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> Senior Embedded Engineer
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