On 04/18/2017 07:42 PM, Vitaly Andrianov wrote:
> On 04/18/2017 08:50 AM, Vitaly Andrianov wrote:
>> On 04/18/2017 06:41 AM, Jan Kiszka wrote:
>>> On 2017-04-17 15:17, Vitaly Andrianov wrote:
>>>> Hi Ralf,
>>>>
>>>> I tried what you proposed:
>>>>
>>>> root@am57xx-evm:~# jailhouse cell load 1 ./loader.bin -a 0 ./inmate.bin
>>>> -a 0x80000000
>>>> Cell "AM57XX-EVM-PDK-LED" can be loaded
>>>> root@am57xx-evm:~# jailhouse cell start 1
>>>> Started cell "AM57XX-EVM-PDK-LED"
>>>>
>>>> That didn't work for me.
>>>>
>>>> I debugged this using CCS debugger. I set a breakpoint to the address
>>>> 0x80000000, and execution stressfully stopped at that address. But it
>>>> looks like instruction cache is not invalidated.
>>>>  From the memory window I can see that the loader.bin and inmate.bin
>>>> code
>>>> are loaded to the memory. I see the correct code from all three views:
>>>> physical, intermediate physical and CPU(virtual).
>>>> But for Disassembly window I can see only loader.bin code is valid
>>>> (address 0x0). Code at address 0x80000000 doesn't correspond to what I
>>>> see at the memory window at the same address.
>>>>
>>>> Do you know what I could do wrong?
>>>
>>> Weird. We explicitly call flush_icache_range in driver/cell.c,
>>> load_image. That can't be nop on the AM57xx, can it?
>>>
>>> Jan
>>>
>> Jan,
>>
>> I disassembled the jailhouse.ko. The flash_icache_range is the
>> v7_coherent_user_range.
>> Actually I don't understand how it works. The jailhouse_cmd_cell_load
>> is running on ARM0 and
>> invalidation is done for L2 and L1 of ARM0. Does the
>> v7_coherent_user_range() also invalidates L1
>> instruction cache for ARM1?
>>
>> Thanks,
>> -Vitaly
>>
> Jan, Ralf,
> 
> I found what was wrong. When I changed the linker address on my test_app
> from 0x0 to 0x80000000, I forgot to change the app's MMU configuration.
> When I fixed the bug everything started to work.
> Except one thing which I still don't understand: the CCS disassembly
> window doesn't show the correct code at the beginning of the 0x80000000
> segment (about first 120 bytes). That confused me and I thought I had an
> instruction cache issue.
Good news! Now the linux-loader should do the same job as well. Just in
case that you don't want to provide you own loader page.

  Ralf
> 
> Sorry for the false alarm.
> 
> Thanks,
> -Vitaly
> 
> 
> 

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