Uses the primary UART console as shared device, but the interrupt will be redirected to the non-root Linux cell.
IVSHMEM virtual PCI device is enabled. Signed-off-by: Ralf Ramsauer <[email protected]> --- configs/dts/inmate-jetson-tx1.dts | 99 ++++++++++++++++++++++++++++++++ configs/jetson-tx1-linux-demo.c | 117 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 216 insertions(+) create mode 100644 configs/dts/inmate-jetson-tx1.dts create mode 100644 configs/jetson-tx1-linux-demo.c diff --git a/configs/dts/inmate-jetson-tx1.dts b/configs/dts/inmate-jetson-tx1.dts new file mode 100644 index 00000000..72511938 --- /dev/null +++ b/configs/dts/inmate-jetson-tx1.dts @@ -0,0 +1,99 @@ +/* + * Jailhouse, a Linux-based partitioning hypervisor + * + * Device tree for Linux inmate test on Jetson TX1 board, + * corresponds to configs/jetson-tx1-linux-demo.c + * + * Copyright (c) OTH Regensburg, 2017 + * + * Authors: + * Ralf Ramsauer <[email protected]> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/dts-v1/; + +/ { + model = "Jailhouse cell on NVIDIA Jetson TX1"; + + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@2 { + compatible = "arm,cortex-a57"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu@3 { + compatible = "arm,cortex-a57"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@50041000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x50041000 0x1000>, + <0x50042000 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&gic>; + }; + + serial@70006000 { + compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <408000000>; + status = "okay"; + }; + + vpci@48000000 { + status = "okay"; + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 152 0>, + <0 0 0 2 &gic GIC_SPI 153 0>, + <0 0 0 3 &gic GIC_SPI 154 0>, + <0 0 0 4 &gic GIC_SPI 155 0>; + reg = <0x48000000 0x100000>; + ranges = + <0x02000000 0x00 0x10000000 0x10000000 0x00 0x10000>; + }; +}; diff --git a/configs/jetson-tx1-linux-demo.c b/configs/jetson-tx1-linux-demo.c new file mode 100644 index 00000000..304956fe --- /dev/null +++ b/configs/jetson-tx1-linux-demo.c @@ -0,0 +1,117 @@ +/* + * Jailhouse, a Linux-based partitioning hypervisor + * + * Configuration for linux-demo inmate on Jetson TX1: + * 2 CPUs, 428M RAM, serial port D + * + * Copyright (c) OTH Regensburg, 2017 + * + * Authors: + * Ralf Ramsauer <[email protected]> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + * Note: the root Linux should be started with "mem=3584M" + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0]) + +#ifndef CONFIG_INMATE_BASE +#define CONFIG_INMATE_BASE 0x0 +#endif + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[4]; + struct jailhouse_irqchip irqchips[2]; + struct jailhouse_pci_device pci_devices[1]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "jetson-tx1-linux-demo", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG | + JAILHOUSE_CELL_DEBUG_CONSOLE, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + + .vpci_irq_base = 152, + + .cpu_reset_address = CONFIG_INMATE_BASE, + }, + + .cpus = { + 0xc, + }, + + .mem_regions = { + /* UART */ { + .phys_start = 0x70006000, + .virt_start = 0x70006000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* RAM */ { + .phys_start = 0x17bef0000, + .virt_start = CONFIG_INMATE_BASE, + .size = 0x10000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA | + JAILHOUSE_MEM_LOADABLE, + }, + /* RAM */ { + .phys_start = 0x161200000, + .virt_start = 0xe8000000, + .size = 0x1acf0000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA | + JAILHOUSE_MEM_LOADABLE, + }, + /* IVSHMEM shared memory region */ { + .phys_start = 0x17bf00000, + .virt_start = 0x17bf00000, + .size = 0x100000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + }, + + .irqchips = { + /* GIC */ { + .address = 0x50041000, + .pin_base = 32, + .pin_bitmap = { + 0, (1 << (36 % 32)), 0, 0 + }, + }, + /* GIC */ { + .address = 0x50041000, + .pin_base = 160, + .pin_bitmap = { + 1 << (152+32 - 160), + }, + }, + }, + + .pci_devices = { + /* 00:00.0 */ { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .bdf = 0x00, + .bar_mask = { + 0xffffff00, 0xffffffff, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, + }, + .shmem_region = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH, + }, + }, +}; -- 2.14.1 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. 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