On 2017-09-13 16:29, Ralf Ramsauer wrote: > If an IRQ is a SGI, bits 10-12 in the IAR of a GICv2 encode the > requesting CPU. > > So far, Jailhouse doesn't set those bits (while it should, refer GICv2 > spec!) so we didn't get hurt. Nevertheless, this hits us when issuing > SGIs on bare-metal applications without jailhouse. This patch properly > decodes SGI IRQ numbers. > > Signed-off-by: Ralf Ramsauer <[email protected]> > --- > inmates/lib/arm-common/include/gic.h | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/inmates/lib/arm-common/include/gic.h > b/inmates/lib/arm-common/include/gic.h > index 6b26cdfc..86c1e389 100644 > --- a/inmates/lib/arm-common/include/gic.h > +++ b/inmates/lib/arm-common/include/gic.h > @@ -43,7 +43,10 @@ > > #define GICD_ISENABLER 0x0100 > > -#define is_sgi_ppi(irqn) ((irqn) < 32) > +#define sgi_id(irqn) ((irqn) & 0x3ff) > +#define sgi_requesting_cpu(irqn) (((irqn) >> 10) & 0x7) That's not correct for gic-v3 then, I assume. Should be made gic-v2 only, but I would actually prefer now a solution (for the demo) that is version agnostic. I that light, we can possibly leave the related support in the hypervisor non-existing.
Jan > +#define is_sgi(irqn) (sgi_id(irqn) < 16) > +#define is_sgi_ppi(irqn) (sgi_id(irqn) < 32) > #define is_spi(irqn) ((irqn) > 31 && (irqn) < 1020) > > #ifndef __ASSEMBLY__ > -- Siemens AG, Corporate Technology, CT RDA ITP SES-DE Corporate Competence Center Embedded Linux -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
