Hello, I am having an issue whilst trying to enable Jailhouse on an Apollo Lake SoC. I was unsure whether to post on here or on IRC but I figured this would be better since then any solution can be archived.
The problem I am getting is relating to an invalid PIO read:
FATAL: Invalid PIO read, port: 400 size: 2
RIP: 0xffffffff8128b2ce RSP: 0xffffc90000073d28 FLAGS: 46
RAX: 0x0000000000000000 RBX: 0x0000000000000400 RCX: 0x00000000000004d1
RDX: 0x0000000000000400 RSI: 0xffffc90000073d9c RDI: 0x0000000000000400
CS: 10 BASE: 0x0000000000000000 AR-BYTES: a09b EFER.LMA 1
CR0: 0x0000000080050033 CR3: 0x0000000001a09000 CR4: 0x00000000003426e0
EFER: 0x0000000000000d01
Parking CPU 2 (Cell: "RootCell")
I have been looking around in this Google group and have tried editing
pio_bitmap as suggested (.pio_bitmap = {0}) and still have the same issue. The
port it seems to be complaining about is the ACPI PM1a_EVT_BLK. From
/proc/ioports:
0400-047f : INT34D2:00
0400-047f : pnp 00:00
0400-0403 : ACPI PM1a_EVT_BLK
0404-0405 : ACPI PM1a_CNT_BLK
0408-040b : ACPI PM_TMR
0420-043f : ACPI GPE0_BLK
0450-0450 : ACPI PM2_CNT_BLK
I am currently stuck on this issue having searched around this group for
solutions and having tried as many as I have found.
Thanks for any help in advance,
Connor.
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ioports
Description: Binary data
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Copyright (c) Siemens AG, 2014-2017
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
* Alternatively, you can use or redistribute this file under the following
* BSD license:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* Configuration for
* created with '/usr/local/libexec/jailhouse/jailhouse config create sysconfig.c'
*
* NOTE: This config expects the following to be appended to your kernel cmdline
* "memmap=0x4200000$0x3b000000"
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
struct {
struct jailhouse_system header;
__u64 cpus[1];
struct jailhouse_memory mem_regions[111];
struct jailhouse_irqchip irqchips[1];
__u8 pio_bitmap[0x2000];
struct jailhouse_pci_device pci_devices[37];
struct jailhouse_pci_capability pci_caps[31];
} __attribute__((packed)) config = {
.header = {
.signature = JAILHOUSE_SYSTEM_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.hypervisor_memory = {
.phys_start = 0x3b000000,
.size = 0x4000000,
},
.debug_console = {
.address = 0x80c00000,
.size = 0x1000,
.flags = JAILHOUSE_CON1_TYPE_8250 |
JAILHOUSE_CON1_ACCESS_MMIO |
JAILHOUSE_CON1_REGDIST_4 |
JAILHOUSE_CON2_TYPE_ROOTPAGE,
},
.platform_info = {
.pci_mmconfig_base = 0xe0000000,
.pci_mmconfig_end_bus = 0xff,
.x86 = {
.pm_timer_address = 0x408,
.vtd_interrupt_limit = 256,
.iommu_units = {
{
.base = 0xfed64000,
.size = 0x1000,
},
{
.base = 0xfed65000,
.size = 0x1000,
},
},
},
},
.root_cell = {
.name = "RootCell",
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.pio_bitmap_size = ARRAY_SIZE(config.pio_bitmap),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
.num_pci_caps = ARRAY_SIZE(config.pci_caps),
},
},
.cpus = {
0x000000000000000f,
},
.mem_regions = {
/* MemRegion: 00000000-00097fff : System RAM */
{
.phys_start = 0x0,
.virt_start = 0x0,
.size = 0x98000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 00100000-00ffffff : System RAM */
{
.phys_start = 0x100000,
.virt_start = 0x100000,
.size = 0xf00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 01000000-01ffffff : Kernel */
{
.phys_start = 0x1000000,
.virt_start = 0x1000000,
.size = 0x1000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 02000000-0fffffff : System RAM */
{
.phys_start = 0x2000000,
.virt_start = 0x2000000,
.size = 0xe000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 12200000-3affffff : System RAM */
{
.phys_start = 0x12200000,
.virt_start = 0x12200000,
.size = 0x28e00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 3f200000-7afd5fff : System RAM */
{
.phys_start = 0x3f200000,
.virt_start = 0x3f200000,
.size = 0x3bdd6000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 7afd6000-7afdcfff : ACPI Tables */
{
.phys_start = 0x7afd6000,
.virt_start = 0x7afd6000,
.size = 0x7000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 7afdd000-7afdffff : ACPI Non-volatile Storage */
{
.phys_start = 0x7afdd000,
.virt_start = 0x7afdd000,
.size = 0x3000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 8000c100-801fffff : dwc_usb3 */
{
.phys_start = 0x8000c100,
.virt_start = 0x8000c100,
.size = 0x1f4000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 80200000-803fffff : PCI Bus 0000:01 */
{
.phys_start = 0x80200000,
.virt_start = 0x80200000,
.size = 0x200000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 80400000-805fffff : PCI Bus 0000:01 */
{
.phys_start = 0x80400000,
.virt_start = 0x80400000,
.size = 0x200000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 80600000-807fffff : PCI Bus 0000:02 */
{
.phys_start = 0x80600000,
.virt_start = 0x80600000,
.size = 0x200000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 80800000-809fffff : PCI Bus 0000:03 */
{
.phys_start = 0x80800000,
.virt_start = 0x80800000,
.size = 0x200000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 80a00000-80bfffff : PCI Bus 0000:03 */
{
.phys_start = 0x80a00000,
.virt_start = 0x80a00000,
.size = 0x200000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 80c00000-80c0001f : serial */
{
.phys_start = 0x80c00000,
.virt_start = 0x80c00000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 80c00200-80c002ff : lpss_priv */
{
.phys_start = 0x80c00200,
.virt_start = 0x80c00200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: a0000000-afffffff : 0000:00:02.0 */
{
.phys_start = 0xa0000000,
.virt_start = 0xa0000000,
.size = 0x10000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b1000000-b1ffffff : 0000:00:03.0 */
{
.phys_start = 0xb1000000,
.virt_start = 0xb1000000,
.size = 0x1000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b2000000-b2ffffff : 0000:00:02.0 */
{
.phys_start = 0xb2000000,
.virt_start = 0xb2000000,
.size = 0x1000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3200000-b321ffff : igb_avb */
{
.phys_start = 0xb3200000,
.virt_start = 0xb3200000,
.size = 0x20000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3221000-b3223fff : igb_avb */
{
.phys_start = 0xb3221000,
.virt_start = 0xb3221000,
.size = 0x3000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3300000-b33fffff : 0000:00:0e.0 */
{
.phys_start = 0xb3300000,
.virt_start = 0xb3300000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3400000-b340ffff : xhci-hcd */
{
.phys_start = 0xb3400000,
.virt_start = 0xb3400000,
.size = 0x10000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3410000-b3411fff : ahci */
{
.phys_start = 0xb3410000,
.virt_start = 0xb3410000,
.size = 0x2000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3418000-b341ffff : 0000:00:00.1 */
{
.phys_start = 0xb3418000,
.virt_start = 0xb3418000,
.size = 0x8000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3420000-b3423fff : 0000:00:0e.0 */
{
.phys_start = 0xb3420000,
.virt_start = 0xb3420000,
.size = 0x4000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3424000-b3425fff : 0000:00:11.0 */
{
.phys_start = 0xb3424000,
.virt_start = 0xb3424000,
.size = 0x2000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b342a000-b342a0ff : 0000:00:1f.1 */
{
.phys_start = 0xb342a000,
.virt_start = 0xb342a000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b342b000-b342bfff : 0000:00:1e.0 */
{
.phys_start = 0xb342b000,
.virt_start = 0xb342b000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b342c000-b342cfff : mmc1 */
{
.phys_start = 0xb342c000,
.virt_start = 0xb342c000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b342d000-b342dfff : 0000:00:1c.0 */
{
.phys_start = 0xb342d000,
.virt_start = 0xb342d000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b342e000-b342efff : mmc0 */
{
.phys_start = 0xb342e000,
.virt_start = 0xb342e000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b342f000-b342ffff : 0000:00:1b.0 */
{
.phys_start = 0xb342f000,
.virt_start = 0xb342f000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3430000-b3430fff : 0000:00:1b.0 */
{
.phys_start = 0xb3430000,
.virt_start = 0xb3430000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3431000-b3431fff : 0000:00:1a.0 */
{
.phys_start = 0xb3431000,
.virt_start = 0xb3431000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3432000-b3432fff : 0000:00:1a.0 */
{
.phys_start = 0xb3432000,
.virt_start = 0xb3432000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3433000-b3433fff : 0000:00:19.2 */
{
.phys_start = 0xb3433000,
.virt_start = 0xb3433000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3434000-b34341ff : lpss_dev */
{
.phys_start = 0xb3434000,
.virt_start = 0xb3434000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3434200-b34342ff : lpss_priv */
{
.phys_start = 0xb3434200,
.virt_start = 0xb3434200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3434800-b3434fff : idma64.14 */
{
.phys_start = 0xb3434800,
.virt_start = 0xb3434800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3435000-b3435fff : 0000:00:19.1 */
{
.phys_start = 0xb3435000,
.virt_start = 0xb3435000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3436000-b34361ff : lpss_dev */
{
.phys_start = 0xb3436000,
.virt_start = 0xb3436000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3436200-b34362ff : lpss_priv */
{
.phys_start = 0xb3436200,
.virt_start = 0xb3436200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3436800-b3436fff : idma64.13 */
{
.phys_start = 0xb3436800,
.virt_start = 0xb3436800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3437000-b3437fff : 0000:00:19.0 */
{
.phys_start = 0xb3437000,
.virt_start = 0xb3437000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3438000-b34381ff : lpss_dev */
{
.phys_start = 0xb3438000,
.virt_start = 0xb3438000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3438200-b34382ff : lpss_priv */
{
.phys_start = 0xb3438200,
.virt_start = 0xb3438200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3438800-b3438fff : idma64.12 */
{
.phys_start = 0xb3438800,
.virt_start = 0xb3438800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3439000-b3439fff : 0000:00:18.3 */
{
.phys_start = 0xb3439000,
.virt_start = 0xb3439000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b343a000-b343a01f : serial */
{
.phys_start = 0xb343a000,
.virt_start = 0xb343a000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b343a200-b343a2ff : lpss_priv */
{
.phys_start = 0xb343a200,
.virt_start = 0xb343a200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b343b000-b343bfff : 0000:00:18.2 */
{
.phys_start = 0xb343b000,
.virt_start = 0xb343b000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b343d000-b343dfff : 0000:00:18.1 */
{
.phys_start = 0xb343d000,
.virt_start = 0xb343d000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b343e000-b343e01f : serial */
{
.phys_start = 0xb343e000,
.virt_start = 0xb343e000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b343e200-b343e2ff : lpss_priv */
{
.phys_start = 0xb343e200,
.virt_start = 0xb343e200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b343e800-b343efff : idma64.9 */
{
.phys_start = 0xb343e800,
.virt_start = 0xb343e800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b343f000-b343ffff : 0000:00:18.0 */
{
.phys_start = 0xb343f000,
.virt_start = 0xb343f000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3440000-b344001f : serial */
{
.phys_start = 0xb3440000,
.virt_start = 0xb3440000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3440200-b34402ff : lpss_priv */
{
.phys_start = 0xb3440200,
.virt_start = 0xb3440200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3440800-b3440fff : idma64.8 */
{
.phys_start = 0xb3440800,
.virt_start = 0xb3440800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3441000-b3441fff : 0000:00:17.3 */
{
.phys_start = 0xb3441000,
.virt_start = 0xb3441000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3442000-b34421ff : lpss_dev */
{
.phys_start = 0xb3442000,
.virt_start = 0xb3442000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3442200-b34422ff : lpss_priv */
{
.phys_start = 0xb3442200,
.virt_start = 0xb3442200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3442800-b3442fff : idma64.7 */
{
.phys_start = 0xb3442800,
.virt_start = 0xb3442800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3443000-b3443fff : 0000:00:17.2 */
{
.phys_start = 0xb3443000,
.virt_start = 0xb3443000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3444000-b34441ff : lpss_dev */
{
.phys_start = 0xb3444000,
.virt_start = 0xb3444000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3444200-b34442ff : lpss_priv */
{
.phys_start = 0xb3444200,
.virt_start = 0xb3444200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3444800-b3444fff : idma64.6 */
{
.phys_start = 0xb3444800,
.virt_start = 0xb3444800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3445000-b3445fff : 0000:00:17.1 */
{
.phys_start = 0xb3445000,
.virt_start = 0xb3445000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3446000-b34461ff : lpss_dev */
{
.phys_start = 0xb3446000,
.virt_start = 0xb3446000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3446200-b34462ff : lpss_priv */
{
.phys_start = 0xb3446200,
.virt_start = 0xb3446200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3446800-b3446fff : idma64.5 */
{
.phys_start = 0xb3446800,
.virt_start = 0xb3446800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3447000-b3447fff : 0000:00:17.0 */
{
.phys_start = 0xb3447000,
.virt_start = 0xb3447000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3448000-b34481ff : lpss_dev */
{
.phys_start = 0xb3448000,
.virt_start = 0xb3448000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3448200-b34482ff : lpss_priv */
{
.phys_start = 0xb3448200,
.virt_start = 0xb3448200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3448800-b3448fff : idma64.4 */
{
.phys_start = 0xb3448800,
.virt_start = 0xb3448800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3449000-b3449fff : 0000:00:16.3 */
{
.phys_start = 0xb3449000,
.virt_start = 0xb3449000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b344a000-b344a1ff : lpss_dev */
{
.phys_start = 0xb344a000,
.virt_start = 0xb344a000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b344a200-b344a2ff : lpss_priv */
{
.phys_start = 0xb344a200,
.virt_start = 0xb344a200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b344a800-b344afff : idma64.3 */
{
.phys_start = 0xb344a800,
.virt_start = 0xb344a800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b344b000-b344bfff : 0000:00:16.2 */
{
.phys_start = 0xb344b000,
.virt_start = 0xb344b000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b344c000-b344c1ff : lpss_dev */
{
.phys_start = 0xb344c000,
.virt_start = 0xb344c000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b344c200-b344c2ff : lpss_priv */
{
.phys_start = 0xb344c200,
.virt_start = 0xb344c200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b344c800-b344cfff : idma64.2 */
{
.phys_start = 0xb344c800,
.virt_start = 0xb344c800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b344d000-b344dfff : 0000:00:16.1 */
{
.phys_start = 0xb344d000,
.virt_start = 0xb344d000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b344e000-b344e1ff : lpss_dev */
{
.phys_start = 0xb344e000,
.virt_start = 0xb344e000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b344e200-b344e2ff : lpss_priv */
{
.phys_start = 0xb344e200,
.virt_start = 0xb344e200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b344e800-b344efff : idma64.1 */
{
.phys_start = 0xb344e800,
.virt_start = 0xb344e800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b344f000-b344ffff : 0000:00:16.0 */
{
.phys_start = 0xb344f000,
.virt_start = 0xb344f000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3450000-b34501ff : lpss_dev */
{
.phys_start = 0xb3450000,
.virt_start = 0xb3450000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3450200-b34502ff : lpss_priv */
{
.phys_start = 0xb3450200,
.virt_start = 0xb3450200,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3450800-b3450fff : idma64.0 */
{
.phys_start = 0xb3450800,
.virt_start = 0xb3450800,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3452000-b34527ff : ahci */
{
.phys_start = 0xb3452000,
.virt_start = 0xb3452000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3453000-b34530ff : ahci */
{
.phys_start = 0xb3453000,
.virt_start = 0xb3453000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3454000-b3454fff : 0000:00:11.0 */
{
.phys_start = 0xb3454000,
.virt_start = 0xb3454000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3455000-b3455fff : 0000:00:0f.2 */
{
.phys_start = 0xb3455000,
.virt_start = 0xb3455000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3456000-b3456fff : 0000:00:0f.1 */
{
.phys_start = 0xb3456000,
.virt_start = 0xb3456000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: b3457000-b3457fff : 0000:00:0f.0 */
{
.phys_start = 0xb3457000,
.virt_start = 0xb3457000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: f8c00000-f8c00158 : apl_gpio.3 */
{
.phys_start = 0xf8c00000,
.virt_start = 0xf8c00000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: f8c40000-f8c40268 : apl_gpio.1 */
{
.phys_start = 0xf8c40000,
.virt_start = 0xf8c40000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: f8c50000-f8c502d0 : apl_gpio.0 */
{
.phys_start = 0xf8c50000,
.virt_start = 0xf8c50000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: f8c70000-f8c70178 : apl_gpio.2 */
{
.phys_start = 0xf8c70000,
.virt_start = 0xf8c70000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe042000-fe043fff : INT34D2:00 */
{
.phys_start = 0xfe042000,
.virt_start = 0xfe042000,
.size = 0x2000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fe044000-fe045fff : INT34D2:00 */
{
.phys_start = 0xfe044000,
.virt_start = 0xfe044000,
.size = 0x2000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fea00000-feafffff : pnp 00:01 */
{
.phys_start = 0xfea00000,
.virt_start = 0xfea00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fed00000-fed003ff : HPET 0 */
{
.phys_start = 0xfed00000,
.virt_start = 0xfed00000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: ff800000-ffffffff : Unusable memory */
{
.phys_start = 0xff800000,
.virt_start = 0xff800000,
.size = 0x800000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 100000000-27fffffff : System RAM */
{
.phys_start = 0x100000000,
.virt_start = 0x100000000,
.size = 0x180000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 7afe0000-7affffff : ACPI DMAR RMRR */
/* PCI device: 00:15.0 */
/* PCI device: 00:15.1 */
{
.phys_start = 0x7afe0000,
.virt_start = 0x7afe0000,
.size = 0x20000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 7b800000-7fffffff : ACPI DMAR RMRR */
/* PCI device: 00:02.0 */
{
.phys_start = 0x7b800000,
.virt_start = 0x7b800000,
.size = 0x4800000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 3f000000-3f1fffff : JAILHOUSE Inmate Memory */
{
.phys_start = 0x3f000000,
.virt_start = 0x3f000000,
.size = 0x200000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
},
.irqchips = {
/* IOAPIC 8, GSI base 0 */
{
.address = 0xfec00000,
.id = 0x1faf8,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
},
.pio_bitmap = {
[ 0/8 ... 0x3f/8] = -1,
[ 0x40/8 ... 0x47/8] = 0xf0, /* PIT */
[ 0x48/8 ... 0x5f/8] = -1,
[ 0x60/8 ... 0x67/8] = 0xec, /* HACK: NMI status/control */
[ 0x68/8 ... 0x6f/8] = -1,
[ 0x70/8 ... 0x77/8] = 0xfc, /* RTC */
[ 0x78/8 ... 0x7f/8] = -1,
[ 0x80/8 ... 0x87/8] = 0xfe, /* Linux: native_io_delay() */
[ 0x88/8 ... 0x3af/8] = -1,
[ 0x3b0/8 ... 0x3df/8] = 0x00, /* VGA */
[ 0x3e0/8 ... 0xcff/8] = -1,
[ 0xd00/8 ... 0xffff/8] = 0, /* HACK: PCI bus */
},
.pci_devices = {
/* PCIDevice: 00:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0x0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:00.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0x1,
.bar_mask = {
0xffff8000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:02.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x10,
.bar_mask = {
0xff000000, 0xffffffff, 0xf0000000,
0xffffffff, 0xffffffc0, 0x00000000,
},
.caps_start = 2,
.num_caps = 4,
.num_msi_vectors = 1,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:03.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0x18,
.bar_mask = {
0xff000000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 6,
.num_caps = 3,
.num_msi_vectors = 1,
.msi_64bits = 1,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:0e.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0x70,
.bar_mask = {
0xffffc000, 0xffffffff, 0x00000000,
0x00000000, 0xfff00000, 0xffffffff,
},
.caps_start = 9,
.num_caps = 3,
.num_msi_vectors = 1,
.msi_64bits = 1,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:0f.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0x78,
.bar_mask = {
0xfffff000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 12,
.num_caps = 3,
.num_msi_vectors = 1,
.msi_64bits = 1,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:0f.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0x79,
.bar_mask = {
0xfffff000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 12,
.num_caps = 3,
.num_msi_vectors = 1,
.msi_64bits = 1,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:0f.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0x7a,
.bar_mask = {
0xfffff000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 12,
.num_caps = 3,
.num_msi_vectors = 1,
.msi_64bits = 1,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:11.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0x88,
.bar_mask = {
0xffffe000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:12.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0x90,
.bar_mask = {
0xffffe000, 0xffffff00, 0xfffffff8,
0xfffffffc, 0xffffffe0, 0xfffff800,
},
.caps_start = 17,
.num_caps = 3,
.num_msi_vectors = 1,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:13.0 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 1,
.domain = 0x0,
.bdf = 0x98,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 20,
.num_caps = 4,
.num_msi_vectors = 1,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:13.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 1,
.domain = 0x0,
.bdf = 0x99,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 20,
.num_caps = 4,
.num_msi_vectors = 1,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:14.0 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xa0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 20,
.num_caps = 4,
.num_msi_vectors = 1,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:15.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xa8,
.bar_mask = {
0xffff0000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 24,
.num_caps = 3,
.num_msi_vectors = 8,
.msi_64bits = 1,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:15.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xa9,
.bar_mask = {
0xffe00000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:16.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xb0,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:16.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xb1,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:16.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xb2,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:16.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xb3,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:17.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xb8,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:17.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xb9,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:17.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xba,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:17.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xbb,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xc0,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xc1,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xc2,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xc3,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:19.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xc8,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:19.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xc9,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:19.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xca,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1a.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xd0,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1b.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xd8,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1c.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xe0,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1e.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xf0,
.bar_mask = {
0xfffff000, 0xffffffff, 0xfffff000,
0xffffffff, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 2,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1f.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xf8,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1f.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0xf9,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0xffffffe0, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 02:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 1,
.domain = 0x0,
.bdf = 0x200,
.bar_mask = {
0xfffe0000, 0x00000000, 0xffffffe0,
0xffffc000, 0x00000000, 0x00000000,
},
.caps_start = 27,
.num_caps = 4,
.num_msi_vectors = 1,
.msi_64bits = 1,
.num_msix_vectors = 5,
.msix_region_size = 0x1000,
.msix_address = 0xb3220000,
},
},
.pci_caps = {
/* PCIDevice: 00:00.1 */
{
.id = 0x1,
.start = 0xd0,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x9,
.start = 0xe0,
.len = 2,
.flags = 0,
},
/* PCIDevice: 00:02.0 */
{
.id = 0x9,
.start = 0x40,
.len = 2,
.flags = 0,
},
{
.id = 0x10,
.start = 0x70,
.len = 60,
.flags = 0,
},
{
.id = 0x5,
.start = 0xac,
.len = 10,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x1,
.start = 0xd0,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
/* PCIDevice: 00:03.0 */
{
.id = 0x10,
.start = 0x70,
.len = 60,
.flags = 0,
},
{
.id = 0x5,
.start = 0xac,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x1,
.start = 0xd0,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
/* PCIDevice: 00:0e.0 */
{
.id = 0x1,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x5,
.start = 0x60,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x10,
.start = 0x70,
.len = 20,
.flags = 0,
},
/* PCIDevice: 00:0f.0 */
/* PCIDevice: 00:0f.1 */
/* PCIDevice: 00:0f.2 */
{
.id = 0x1,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x5,
.start = 0x8c,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x9,
.start = 0xa4,
.len = 2,
.flags = 0,
},
/* PCIDevice: 00:11.0 */
/* PCIDevice: 00:15.1 */
/* PCIDevice: 00:16.0 */
/* PCIDevice: 00:16.1 */
/* PCIDevice: 00:16.2 */
/* PCIDevice: 00:16.3 */
/* PCIDevice: 00:17.0 */
/* PCIDevice: 00:17.1 */
/* PCIDevice: 00:17.2 */
/* PCIDevice: 00:17.3 */
/* PCIDevice: 00:18.0 */
/* PCIDevice: 00:18.1 */
/* PCIDevice: 00:18.2 */
/* PCIDevice: 00:18.3 */
/* PCIDevice: 00:19.0 */
/* PCIDevice: 00:19.1 */
/* PCIDevice: 00:19.2 */
/* PCIDevice: 00:1a.0 */
/* PCIDevice: 00:1b.0 */
/* PCIDevice: 00:1c.0 */
/* PCIDevice: 00:1e.0 */
{
.id = 0x1,
.start = 0x80,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x9,
.start = 0x90,
.len = 2,
.flags = 0,
},
/* PCIDevice: 00:12.0 */
{
.id = 0x5,
.start = 0x80,
.len = 10,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x1,
.start = 0x70,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x12,
.start = 0xa8,
.len = 2,
.flags = 0,
},
/* PCIDevice: 00:13.0 */
/* PCIDevice: 00:13.1 */
/* PCIDevice: 00:14.0 */
{
.id = 0x10,
.start = 0x40,
.len = 60,
.flags = 0,
},
{
.id = 0x5,
.start = 0x80,
.len = 10,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0xd,
.start = 0x90,
.len = 2,
.flags = 0,
},
{
.id = 0x1,
.start = 0xa0,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
/* PCIDevice: 00:15.0 */
{
.id = 0x1,
.start = 0x70,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x5,
.start = 0x80,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x9,
.start = 0x90,
.len = 2,
.flags = 0,
},
/* PCIDevice: 02:00.0 */
{
.id = 0x1,
.start = 0x40,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x5,
.start = 0x50,
.len = 24,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x11,
.start = 0x70,
.len = 12,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = 0x10,
.start = 0xa0,
.len = 60,
.flags = 0,
},
},
};
Initializing Jailhouse hypervisor v0.7 (99-ge69f9ec-dirty) on CPU 1
Code location: 0xfffffffff0000060
Using xAPIC
Page pool usage after early setup: mem 77/16328, remap 65/131072
Initializing processors:
CPU 1... (APIC ID 2) OK
CPU 2... (APIC ID 4) OK
CPU 3... (APIC ID 6) OK
CPU 0... (APIC ID 0) OK
DMAR unit @0xfed64000/0x1000
DMAR unit @0xfed65000/0x1000
Reserving 120 interrupt(s) for device faf8 at index 0
Adding PCI device 00:00.0 to cell "RootCell"
Adding PCI device 00:00.1 to cell "RootCell"
Adding PCI device 00:02.0 to cell "RootCell"
Reserving 1 interrupt(s) for device 0010 at index 120
Adding PCI device 00:03.0 to cell "RootCell"
Reserving 1 interrupt(s) for device 0018 at index 121
Adding PCI device 00:0e.0 to cell "RootCell"
Reserving 1 interrupt(s) for device 0070 at index 122
Adding PCI device 00:0f.0 to cell "RootCell"
Reserving 1 interrupt(s) for device 0078 at index 123
Adding PCI device 00:0f.1 to cell "RootCell"
Reserving 1 interrupt(s) for device 0079 at index 124
Adding PCI device 00:0f.2 to cell "RootCell"
Reserving 1 interrupt(s) for device 007a at index 125
Adding PCI device 00:11.0 to cell "RootCell"
Adding PCI device 00:12.0 to cell "RootCell"
Reserving 1 interrupt(s) for device 0090 at index 126
Adding PCI device 00:13.0 to cell "RootCell"
Reserving 1 interrupt(s) for device 0098 at index 127
Adding PCI device 00:13.1 to cell "RootCell"
Reserving 1 interrupt(s) for device 0099 at index 128
Adding PCI device 00:14.0 to cell "RootCell"
Reserving 1 interrupt(s) for device 00a0 at index 129
Adding PCI device 00:15.0 to cell "RootCell"
Reserving 8 interrupt(s) for device 00a8 at index 130
Adding PCI device 00:15.1 to cell "RootCell"
Adding PCI device 00:16.0 to cell "RootCell"
Adding PCI device 00:16.1 to cell "RootCell"
Adding PCI device 00:16.2 to cell "RootCell"
Adding PCI device 00:16.3 to cell "RootCell"
Adding PCI device 00:17.0 to cell "RootCell"
Adding PCI device 00:17.1 to cell "RootCell"
Adding PCI device 00:17.2 to cell "RootCell"
Adding PCI device 00:17.3 to cell "RootCell"
Adding PCI device 00:18.0 to cell "RootCell"
Adding PCI device 00:18.1 to cell "RootCell"
Adding PCI device 00:18.2 to cell "RootCell"
Adding PCI device 00:18.3 to cell "RootCell"
Adding PCI device 00:19.0 to cell "RootCell"
Adding PCI device 00:19.1 to cell "RootCell"
Adding PCI device 00:19.2 to cell "RootCell"
Adding PCI device 00:1a.0 to cell "RootCell"
Adding PCI device 00:1b.0 to cell "RootCell"
Adding PCI device 00:1c.0 to cell "RootCell"
Adding PCI device 00:1e.0 to cell "RootCell"
Adding PCI device 00:1f.0 to cell "RootCell"
Adding PCI device 00:1f.1 to cell "RootCell"
Adding PCI device 02:00.0 to cell "RootCell"
Reserving 5 interrupt(s) for device 0200 at index 138
Page pool usage after late setup: mem 232/16328, remap 65611/131072
FATAL: Invalid PIO read, port: 400 size: 2
RIP: 0xffffffff8128b2ce RSP: 0xffffc90000073d28 FLAGS: 46
RAX: 0x0000000000000000 RBX: 0x0000000000000400 RCX: 0x00000000000004d1
RDX: 0x0000000000000400 RSI: 0xffffc90000073d9c RDI: 0x0000000000000400
CS: 10 BASE: 0x0000000000000000 AR-BYTES: a09b EFER.LMA 1
CR0: 0x0000000080050033 CR3: 0x0000000001a09000 CR4: 0x00000000003426e0
EFER: 0x0000000000000d01
Parking CPU 2 (Cell: "RootCell")
