Branch: refs/heads/coverity_scan
Home: https://github.com/siemens/jailhouse
Commit: 38ab72ecf1c93fd630ef94cef42da3f089d2cfab
https://github.com/siemens/jailhouse/commit/38ab72ecf1c93fd630ef94cef42da3f089d2cfab
Author: Jan Kiszka <[email protected]>
Date: 2017-10-20 (Fri, 20 Oct 2017)
Changed paths:
M hypervisor/arch/x86/svm.c
M hypervisor/arch/x86/vcpu.c
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: Relocate parking code page
This step prepares for configurable cell reset addresses. In order to
enable them, we need a stable parking code address so that we do not
need to generate per-cell mappings for this purpose.
Simply place the parking loop at address 0. Use a regular SIPI vector 0
for resetting the affected CPUs. This means on Intel that we have to
issue the DEBUGCTL reset separately in vcpu_park because we no longer
take the APIC_BSP_PSEUDO_SIPI path.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 8457e83186f157e7ebd30d75e6e652b2ee61d563
https://github.com/siemens/jailhouse/commit/8457e83186f157e7ebd30d75e6e652b2ee61d563
Author: Jan Kiszka <[email protected]>
Date: 2017-10-22 (Sun, 22 Oct 2017)
Changed paths:
M configs/apic-demo.c
M configs/e1000-demo.c
M configs/ioapic-demo.c
M configs/ivshmem-demo.c
M configs/linux-x86-demo.c
M configs/pci-demo.c
M configs/smp-demo.c
M configs/tiny-demo.c
M hypervisor/arch/x86/svm.c
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86, configs: Make CPU reset address configurable
Analogously to ARM, this makes the reset address of x86 CPUs definable
via jailhouse_cell_desc.cpu_reset_address. In order to keep the existing
demo inmates alive, all related config files define cpu_reset_address to
0xffff0 which was hard-coded into the hypervisor so far.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 044114743141bfd171df5481b0efab51a0c0b68d
https://github.com/siemens/jailhouse/commit/044114743141bfd171df5481b0efab51a0c0b68d
Author: Henning Schild <[email protected]>
Date: 2017-10-22 (Sun, 22 Oct 2017)
Changed paths:
M README.md
Log Message:
-----------
README: use icon for webchat link
Signed-off-by: Henning Schild <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 00469194a1d8ef718e30b9239ffffaf762eaf386
https://github.com/siemens/jailhouse/commit/00469194a1d8ef718e30b9239ffffaf762eaf386
Author: Otavio Pontes <[email protected]>
Date: 2017-10-31 (Tue, 31 Oct 2017)
Changed paths:
M hypervisor/arch/x86/control.c
M hypervisor/arch/x86/include/asm/jailhouse_hypercall.h
M inmates/tools/x86/linux-loader.c
M tools/jailhouse-cell-linux
Log Message:
-----------
x86: Export PCI mmconfig base address to Linux inmates
In order to access the PCI express extended configuration space, a linux
inmate needs to have access to the PCI mmconfig base address. As inmates
doesn't have access to this information using ACPI, we need to export it
using the cell comm_region.
Note that the updates in Linux kernel used as inmate are also necessary
in order to use the exported value as the PCI mmconfig base address.
Signed-off-by: Otavio Pontes <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: dc6cf30c82876d973c528c487223d36e6443fabe
https://github.com/siemens/jailhouse/commit/dc6cf30c82876d973c528c487223d36e6443fabe
Author: Jan Kiszka <[email protected]>
Date: 2017-10-31 (Tue, 31 Oct 2017)
Changed paths:
M Documentation/debug-output.md
M README.md
M configs/apic-demo.c
M configs/e1000-demo.c
M configs/ioapic-demo.c
M configs/ivshmem-demo.c
M configs/linux-x86-demo.c
M configs/pci-demo.c
M configs/smp-demo.c
M configs/tiny-demo.c
M inmates/lib/x86/header-32.S
M inmates/lib/x86/header.S
M inmates/lib/x86/inmate.h
M inmates/lib/x86/inmate.lds
M inmates/lib/x86/smp.c
M inmates/tools/x86/linux-loader.c
M tools/jailhouse-cell-linux
Log Message:
-----------
inmates, configs, docs: x86: Locate inmates at address 0
This simplifies the startup code and avoids having to specify the load
address explicitly, aligning x86 with ARM.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: e330e2082bbcebb079dd8b1cf14a4c7bc5e191da
https://github.com/siemens/jailhouse/commit/e330e2082bbcebb079dd8b1cf14a4c7bc5e191da
Author: Jan Kiszka <[email protected]>
Date: 2017-11-01 (Wed, 01 Nov 2017)
Changed paths:
M hypervisor/arch/x86/setup.c
Log Message:
-----------
x86: Fix general protection fault on restoring TR
arch_cpu_restore can run concurrently on multiple CPUs, but our
modifications to the GDT in order to reload Linux TR requires that a
couple of instructions run atomically. Namely, loading TR will set the
busy flag in the descriptor again which may race with another CPU just
trying to load from that descriptor as well. Putting everything under a
spinlock resolves the race.
The effect of this bug were sporadic general protection faults (#13)
while disabling Jailhouse or when enabling it failed.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 3bbbe099e6fde23878addad71f7160d3170367d6
https://github.com/siemens/jailhouse/commit/3bbbe099e6fde23878addad71f7160d3170367d6
Author: Jan Kiszka <[email protected]>
Date: 2017-11-01 (Wed, 01 Nov 2017)
Changed paths:
M hypervisor/arch/x86/setup.c
Log Message:
-----------
x86: Fix arch_cpu_restore for PCID enabled systems
Reorder reloading of cr3 and cr4 in case the latter enables PCID (which
Jailhouse does not use) and cr3 should be fully evaluated under that
feature.
Fixes a protection fault when disabling Jailhouse on PCID-enabled
systems (since kernel 4.14).
Signed-off-by: Jan Kiszka <[email protected]>
Commit: c535fb580bd3c06056baa0ee416328c809f34521
https://github.com/siemens/jailhouse/commit/c535fb580bd3c06056baa0ee416328c809f34521
Author: Jan Kiszka <[email protected]>
Date: 2017-11-04 (Sat, 04 Nov 2017)
Changed paths:
M hypervisor/paging.c
Log Message:
-----------
core: Reindent paging_gvirt2gphys
No functional changes.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 1c0b64d39203b4c5724ae105060227ba8c4e4767
https://github.com/siemens/jailhouse/commit/1c0b64d39203b4c5724ae105060227ba8c4e4767
Author: Jan Kiszka <[email protected]>
Date: 2017-11-04 (Sat, 04 Nov 2017)
Changed paths:
M hypervisor/include/jailhouse/paging.h
M hypervisor/paging.c
Log Message:
-----------
core: Allow to declare paging disabled via guest_paging_structures
This simplifies the implementation of non-paged mode for the only user
of paging_get_guest_pages that passes non-NULL guest_paging_structures,
namely x86.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 352200362ecd327303654f278de1efe7add41e7c
https://github.com/siemens/jailhouse/commit/352200362ecd327303654f278de1efe7add41e7c
Author: Jan Kiszka <[email protected]>
Date: 2017-11-04 (Sat, 04 Nov 2017)
Changed paths:
M hypervisor/arch/x86/include/asm/paging_modes.h
M hypervisor/arch/x86/paging.c
M hypervisor/arch/x86/svm.c
Log Message:
-----------
x86: Drop realmode_paging description
Can now be encoded by setting root_paging to NULL.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 42d2bbd8a925fe7f5a40683ffbd9b5e29d4bbfdc
https://github.com/siemens/jailhouse/commit/42d2bbd8a925fe7f5a40683ffbd9b5e29d4bbfdc
Author: Jan Kiszka <[email protected]>
Date: 2017-11-04 (Sat, 04 Nov 2017)
Changed paths:
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: vmx: Add support for MMIO while paging is disabled
Aligns vmx with svm.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: cfc739900c2d7299b6df09ace8b75c75e2ec58ec
https://github.com/siemens/jailhouse/commit/cfc739900c2d7299b6df09ace8b75c75e2ec58ec
Author: Jan Kiszka <[email protected]>
Date: 2017-11-04 (Sat, 04 Nov 2017)
Changed paths:
M hypervisor/arch/x86/include/asm/paging_modes.h
M hypervisor/arch/x86/include/asm/percpu.h
M hypervisor/arch/x86/include/asm/svm.h
M hypervisor/arch/x86/include/asm/vcpu.h
M hypervisor/arch/x86/paging.c
M hypervisor/arch/x86/svm.c
M hypervisor/arch/x86/vcpu.c
M hypervisor/arch/x86/vmx.c
Log Message:
-----------
x86: Add support for PAE guest paging mode
This completes the guest paging support with the last missing mode: PAE.
While most guests should not use this legacy mode anymore, at least
Zephyr does. Moreover, supporting this last missing mode allows to drop
the error handling around vcpu_get_guest_paging_structs.
The implementation is complicated on Intel because these CPUs cache the
page directory pointer table in registers, and we can't use the generic
reading from guest memory. In contrast, AMD performs no such caching.
Therefore, we have to use a vendor-specific get_entry handler for the
top level paging.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 909d8574d70e824092658293a1c56498319065d2
https://github.com/siemens/jailhouse/commit/909d8574d70e824092658293a1c56498319065d2
Author: Jan Kiszka <[email protected]>
Date: 2017-11-06 (Mon, 06 Nov 2017)
Changed paths:
M hypervisor/arch/x86/ioapic.c
Log Message:
-----------
x86: Grant read access to reserved IOAPIC registers
Depending on the IOAPIC version, guests may try to read further
information from them. Reading is harmless, so permit the access, even
simplifying the code.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 32e4b975cdcd7f5a2f3d8eb1ee62ceabd24ef038
https://github.com/siemens/jailhouse/commit/32e4b975cdcd7f5a2f3d8eb1ee62ceabd24ef038
Author: Jan Kiszka <[email protected]>
Date: 2017-11-06 (Mon, 06 Nov 2017)
Changed paths:
M hypervisor/arch/x86/ioapic.c
Log Message:
-----------
x86: Ignore accesses to unassigned IOAPIC pins
Do not stop a cell CPU that accesses an IOAPIC redirection table entry
for a pin that it does not own. Rather ignore the access, returning 0 on
reads. This behavior is in line with how we handle GIC accesses on ARM.
It allows guests like Linux to keep their usual IOAPIC initialization
code as-is which may first of all masks all pins of the chip.
Signed-off-by: Jan Kiszka <[email protected]>
Compare:
https://github.com/siemens/jailhouse/compare/2be7ea62732d...32e4b975cdcd
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