From: Ruediger Fichter <[email protected]>
This patch adds:
- root cell configuration
- UART demo configuration
- Linux demo configuration
- Inmate Device Tree for emCON-RZ/G1E
for Renesas RZ/G1E (emCON-RZ/G1E from emtrion).
Signed-off-by: Ruediger Fichter <[email protected]>
Signed-off-by: Jan von Wiarda <[email protected]>
---
configs/dts/inmate-emtrion-emconrzg1e.dts | 166 ++++++++++++++++++++
configs/emtrion-rzg1e-linux-demo.c | 156 +++++++++++++++++++
configs/emtrion-rzg1e-uart-demo.c | 57 +++++++
configs/emtrion-rzg1e.c | 244 ++++++++++++++++++++++++++++++
4 files changed, 623 insertions(+)
create mode 100644 configs/dts/inmate-emtrion-emconrzg1e.dts
create mode 100644 configs/emtrion-rzg1e-linux-demo.c
create mode 100644 configs/emtrion-rzg1e-uart-demo.c
create mode 100644 configs/emtrion-rzg1e.c
diff --git a/configs/dts/inmate-emtrion-emconrzg1e.dts
b/configs/dts/inmate-emtrion-emconrzg1e.dts
new file mode 100644
index 0000000..7b2e99a
--- /dev/null
+++ b/configs/dts/inmate-emtrion-emconrzg1e.dts
@@ -0,0 +1,166 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Device tree for Linux inmate test on emCON-RZ/G1E board,
+ * corresponds to configs/emtrion-emconrzg1e-linux-demo.c
+ *
+ * Copyright (c) emtrion GmbH, 2017
+ *
+ * Authors:
+ * Ruediger Fichter <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a7745-sysc.h>
+
+/dts-v1/;
+
+/memreserve/ 0x0000000070000000 0x0000000000002000;
+/ {
+ model = "Jailhouse cell on emCON-RZ/G1E";
+ compatible = "emtrion,emconrzg1e", "renesas,r8a7745";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ i2c2 = "/i2c@e6530000";
+ serial4 = "/serial@e6ee0000";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ enable-method = "psci";
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clock-frequency = <0x3b9aca00>;
+ power-domains = <0x2 0x5>;
+ clocks = <0x3>;
+ operating-points = <0xf4240 0xf4240>;
+ next-level-cache = <0x4>;
+ linux,phandle = <0x5>;
+ phandle = <0x5>;
+ };
+ };
+
+ memory@70000000 {
+ device_type = "memory";
+ reg = <0x0 0x70000000 0x0 0x0bef0000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySC4,115200 root=/dev/sda1 rootwait
+ ip=dhcp loglevel=8 vt.global_cursor_default=0
+ consoleblank=0";
+ stdout-path = "/serial@e6ee0000";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ vcc_sdhi0: regulator@0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-boot-on;
+ regulator-always-on;
+
+ };
+
+ vccq_sdhi0: regulator@1 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x0 0xf1001000 0x0 0x1000>,
+ <0x0 0xf1002000 0x0 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7745-sysc";
+ reg = <0 0xe6180000 0 0x0200>;
+ #power-domain-cells = <1>;
+ };
+
+ pfc: pin-controller@e6060000 {
+ compatible = "renesas,pfc-r8a7745";
+ reg = <0x0 0xe6060000 0x0 0x11c>;
+ #gpio-range-cells = <0x3>;
+ linux,phandle = <0x7>;
+ phandle = <0x7>;
+
+ serial4 {
+ renesas,groups = "scif4_data_c";
+ renesas,function = "scif4";
+ linux,phandle = <0x12>;
+ phandle = <0x12>;
+ };
+
+ sdhi0_pins: sd0 {
+ renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
+ "sdhi0_cd", "sdhi0_wp";
+ renesas,function = "sdhi0";
+ };
+ };
+
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7745", "renesas,scif";
+ reg = <0 0xe6ee0000 0 0x40>;
+ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "okay";
+ pinctrl-0 = <0x12>;
+ pinctrl-names = "default";
+ };
+
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7745";
+ reg = <0 0xee100000 0 0x200>;
+ interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "okay";
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ };
+
+ i2c2: i2c@e6530000 {
+ compatible = "renesas,i2c-r8a7745";
+ reg = <0 0xe6530000 0 0x40>;
+ interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ };
+};
diff --git a/configs/emtrion-rzg1e-linux-demo.c
b/configs/emtrion-rzg1e-linux-demo.c
new file mode 100644
index 0000000..9d943b6
--- /dev/null
+++ b/configs/emtrion-rzg1e-linux-demo.c
@@ -0,0 +1,156 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for linux-demo inmate on emCON-RZ/G1E:
+ * 1 CPU, 64M RAM, I2C bus I2C2, serial port SCIF4, SDHI0
+ *
+ * Copyright (c) emtrion GmbH, 2017
+ *
+ * Authors:
+ * Ruediger Fichter <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[10];
+ struct jailhouse_irqchip irqchips[3];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "emtrion-emconrzg1e-linux-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ /* .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .vpci_irq_base = 123, */
+ },
+
+ .cpus = {
+ 0x2,
+ },
+
+ .mem_regions = {
+ /* RST, MODEMR */ {
+ .phys_start = 0xe6160060,
+ .virt_start = 0xe6160060,
+ .size = 0x4,
+ .flags = JAILHOUSE_MEM_READ |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* Generic Counter */ {
+ .phys_start = 0xe6080000,
+ .virt_start = 0xe6080000,
+ .size = 0x40,
+ .flags = JAILHOUSE_MEM_READ |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* PFC (HACK) */ {
+ .phys_start = 0xe6060000,
+ .virt_start = 0xe6060000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* SYSC (HACK) */ {
+ .phys_start = 0xe6180000,
+ .virt_start = 0xe6180000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* SCIF4 */ {
+ .phys_start = 0xe6ee0000,
+ .virt_start = 0xe6ee0000,
+ .size = 0x400,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32 |
+ JAILHOUSE_MEM_IO_16 | JAILHOUSE_MEM_IO_8,
+ },
+ /* SDHI0: SDC */ {
+ .phys_start = 0xee100000,
+ .virt_start = 0xee100000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* I2C2 */ {
+ .phys_start = 0xe6530000,
+ .virt_start = 0xe6530000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* RAM */ {
+ .phys_start = 0x7bef0000,
+ .virt_start = 0,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* RAM */ {
+ .phys_start = 0x70000000,
+ .virt_start = 0x70000000,
+ .size = 0xbef0000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
+ JAILHOUSE_MEM_LOADABLE,
+ },
+ /* IVSHMEM shared memory region */ {
+ .phys_start = 0x7bf00000,
+ .virt_start = 0x7bf00000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */ {
+ .address = 0xf1001000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 1 << (24+32 - 32), /* SCIF4 */
+ },
+ },
+ /* GIC */ {
+ .address = 0xf1001000,
+ .pin_base = 160,
+ .pin_bitmap = {
+ 0, 1 << (165+32 - 192) /* SDHI0 */
+ },
+ },
+ /* GIC */ {
+ .address = 0xf1001000,
+ .pin_base = 288,
+ .pin_bitmap = {
+ 1 << (286+32 - 288), /* I2C2 */
+ },
+ },
+ },
+
+ .pci_devices = {
+ /* 00:00.0 */ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .bdf = 0x00,
+ .bar_mask = {
+ 0xffffff00, 0xffffffff, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000,
+ },
+ .shmem_region = 4,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
+ },
+ },
+};
diff --git a/configs/emtrion-rzg1e-uart-demo.c
b/configs/emtrion-rzg1e-uart-demo.c
new file mode 100644
index 0000000..2e4787e
--- /dev/null
+++ b/configs/emtrion-rzg1e-uart-demo.c
@@ -0,0 +1,57 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for uart-demo inmate on emCON-RZ/G1E:
+ * 1 CPU, 64K RAM, serial ports SCIF4, CCU
+ *
+ * Copyright (c) emtrion GmbH, 2017
+ *
+ * Authors:
+ * Ruediger Fichter <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[2];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "emtrion-emconrzg1e-uart-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ },
+
+ .cpus = {
+ 0x2,
+ },
+
+ .mem_regions = {
+ /* SCIF4 */ {
+ .phys_start = 0xe6ee0000,
+ .virt_start = 0xe6ee0000,
+ .size = 0x400,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_8 |
+ JAILHOUSE_MEM_IO_16 | JAILHOUSE_MEM_IO_32,
+ },
+ /* RAM */ {
+ .phys_start = 0x7bff0000,
+ .virt_start = 0,
+ .size = 0x00010000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ }
+};
diff --git a/configs/emtrion-rzg1e.c b/configs/emtrion-rzg1e.c
new file mode 100644
index 0000000..b32c693
--- /dev/null
+++ b/configs/emtrion-rzg1e.c
@@ -0,0 +1,244 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Test configuration for emtrion's emCON-RZ/G1E board
+ * (RZ/G1E dual-core Cortex-A7, 1G RAM)
+ *
+ * Copyright (c) emtrion GmbH, 2017
+ *
+ * Authors:
+ * Ruediger Fichter <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[19];
+ struct jailhouse_irqchip irqchips[3];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .hypervisor_memory = {
+ .phys_start = 0x7c000000,
+ .size = 0x4000000,
+ },
+ .debug_console = {
+ .address = 0xe62d0000,
+ .size = 0x1000,
+ .clock_reg = 0xe615014c,
+ .gate_nr = 13,
+ /* .divider = 0x2e, */
+ .flags = JAILHOUSE_CON1_TYPE_HSCIF |
+ JAILHOUSE_CON1_ACCESS_MMIO |
+ JAILHOUSE_CON1_REGDIST_4 |
+ JAILHOUSE_CON2_TYPE_ROOTPAGE,
+ },
+ .platform_info = {
+ /* .pci_mmconfig_base = 0x2000000,
+ .pci_mmconfig_end_bus = 0,
+ .pci_is_virtual = 1, */
+ .arm = {
+ .gic_version = 2,
+ .gicd_base = 0xf1001000,
+ .gicc_base = 0xf1002000,
+ .gich_base = 0xf1004000,
+ .gicv_base = 0xf1006000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "emCON-RZ/G1E",
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ /* .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .vpci_irq_base = 108, */
+ },
+ },
+
+ .cpus = {
+ 0x3,
+ },
+
+ .mem_regions = {
+ /* CPG */ {
+ .phys_start = 0xe6150000,
+ .virt_start = 0xe6150000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* APMU */ {
+ .phys_start = 0xe6151000,
+ .virt_start = 0xe6151000,
+ .size = 0xf000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* IRQC */ {
+ .phys_start = 0xe61c0000,
+ .virt_start = 0xe61c0000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* CMT0 */ {
+ .phys_start = 0xffca0000,
+ .virt_start = 0xffca0000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* CMT1 */ {
+ .phys_start = 0xe6130000,
+ .virt_start = 0xe6130000,
+ .size = 0x2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* TMU0 */ {
+ .phys_start = 0xe61e0000,
+ .virt_start = 0xe61e0000,
+ .size = 0x400,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO | JAILHOUSE_MEM_IO_32,
+ },
+ /* HSCIF2 */ {
+ .phys_start = 0xe62d0000,
+ .virt_start = 0xe62d0000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* EtherAVB */ {
+ .phys_start = 0xe6800000,
+ .virt_start = 0xe6800000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* MMCIF: eMMC */ {
+ .phys_start = 0xee200000,
+ .virt_start = 0xee200000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* USB0 */ {
+ .phys_start = 0xee080000,
+ .virt_start = 0xee080000,
+ .size = 0x00020000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* VSPDU */ {
+ .phys_start = 0xfe930000,
+ .virt_start = 0xfe930000,
+ .size = 0x00008000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* DU */ {
+ .phys_start = 0xfeb00000,
+ .virt_start = 0xfeb00000,
+ .size = 0x00040000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* CAN0 */ {
+ .phys_start = 0xe6e80000,
+ .virt_start = 0xe6e80000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* CAN1 */ {
+ .phys_start = 0xe6e88000,
+ .virt_start = 0xe6e88000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* I2C0 */ {
+ .phys_start = 0xe6508000,
+ .virt_start = 0xe6508000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* I2C1 */ {
+ .phys_start = 0xe6530000,
+ .virt_start = 0xe6530000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* I2C2 */ {
+ .phys_start = 0xe6540000,
+ .virt_start = 0xe6540000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* RAM */ {
+ .phys_start = 0x40000000,
+ .virt_start = 0x40000000,
+ .size = 0x3bf00000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* IVSHMEM shared memory region */ {
+ .phys_start = 0x7bf00000,
+ .virt_start = 0x7bf00000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */ {
+ .address = 0xf1001000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+ },
+ },
+ /* GIC */ {
+ .address = 0xf1001000,
+ .pin_base = 160,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+ },
+ },
+ /* GIC */ {
+ .address = 0xf1001000,
+ .pin_base = 288,
+ .pin_bitmap = {
+ 0xffffffff
+ },
+ },
+ },
+
+ .pci_devices = {
+ /* 00:00.0 */ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .bdf = 0x00,
+ .bar_mask = {
+ 0xffffff00, 0xffffffff, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000,
+ },
+ .shmem_region = 16,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
+ },
+ },
+};
--
2.11.0
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