ARM inmates make use of hypervisor's sysregs accessors and helpers. In
order to entirely decouple the hypervisor code from inmate code, let's
duplicate some of those definitions, but only those that are really in
use.

Signed-off-by: Ralf Ramsauer <[email protected]>
Signed-off-by: Jean-Philippe Brucker <[email protected]>
Signed-off-by: Antonios Motakis <[email protected]>
Cc: Jean-Philippe Brucker <[email protected]>
Cc: Jan Kiszka <[email protected]>
Cc: Antonios Motakis <[email protected]>
---
 inmates/lib/arm/include/asm/sysregs.h | 76 +++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 inmates/lib/arm/include/asm/sysregs.h

diff --git a/inmates/lib/arm/include/asm/sysregs.h 
b/inmates/lib/arm/include/asm/sysregs.h
new file mode 100644
index 00000000..7c285923
--- /dev/null
+++ b/inmates/lib/arm/include/asm/sysregs.h
@@ -0,0 +1,76 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) OTH Regensburg, 2017
+ *
+ * Authors:
+ *  Ralf Ramsauer <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2.  See
+ * the COPYING file in the top-level directory.
+ *
+ * Alternatively, you can use or redistribute this file under the following
+ * BSD license:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* The following definitions are inspired by
+ * hypervisor/arch/arm/include/asm/sysregs.h */
+
+#define VBAR           SYSREG_32(0, c12, c0, 0)
+#define CNTFRQ_EL0     SYSREG_32(0, c14, c0, 0)
+#define CNTV_TVAL_EL0  SYSREG_32(0, c14, c3, 0)
+#define CNTV_CTL_EL0   SYSREG_32(0, c14, c3, 1)
+#define CNTPCT_EL0     SYSREG_64(0, c14)
+
+#define SYSREG_32(...) 32, __VA_ARGS__
+#define SYSREG_64(...) 64, __VA_ARGS__
+
+#define _arm_write_sysreg(size, ...) arm_write_sysreg_ ## size(__VA_ARGS__)
+#define arm_write_sysreg(...) _arm_write_sysreg(__VA_ARGS__)
+
+#define _arm_read_sysreg(size, ...) arm_read_sysreg_ ## size(__VA_ARGS__)
+#define arm_read_sysreg(...) _arm_read_sysreg(__VA_ARGS__)
+
+#ifndef __ASSEMBLY__
+asm(".arch_extension virt\n");
+
+#define arm_write_sysreg_32(op1, crn, crm, op2, val) \
+       asm volatile ("mcr      p15, "#op1", %0, "#crn", "#crm", "#op2"\n" \
+                       : : "r"((u32)(val)))
+
+#define arm_read_sysreg_32(op1, crn, crm, op2, val) \
+       asm volatile ("mrc      p15, "#op1", %0, "#crn", "#crm", "#op2"\n" \
+                       : "=r"((u32)(val)))
+#define arm_read_sysreg_64(op1, crm, val) \
+       asm volatile ("mrrc     p15, "#op1", %Q0, %R0, "#crm"\n" \
+                       : "=r"((u64)(val)))
+
+#else /* __ASSEMBLY__ */
+
+#define arm_write_sysreg_32(op1, crn, crm, op2, reg) \
+       mcr     p15, op1, reg, crn, crm, op2
+
+#endif /* __ASSEMBLY__ */
-- 
2.15.1

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