On 2018-01-12 01:22, Gustavo Lima Chaves wrote:
> From: Otavio Pontes <[email protected]>
> 
> If one has CONFIG_PCIEAER=y enabled in Linux inmates, from
> pci_device_add() -> pci_init_capabilities() -> pci_aer_init() ->
> pci_cleanup_aer_error_status_regs(), there *will* we writes to the AER

s/we/be/

> capability in it and, as it is now, Jailhouse will park the cell right
> away. This commit makes the capability size guessed right and makes it
> read/writable.
> 
> Finally, partitioning-wise this should not hurt, since the capability is
> bound to affect its function, only.

The last statement is not correct as the succeeding patches show.

> 
> Signed-off-by: Gustavo Lima Chaves <[email protected]>

Ideally, we have both signed-offs in the order of handling.

> ---
>  tools/jailhouse-config-create | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/jailhouse-config-create b/tools/jailhouse-config-create
> index ce2affce..505e8050 100755
> --- a/tools/jailhouse-config-create
> +++ b/tools/jailhouse-config-create
> @@ -226,6 +226,7 @@ class PCICapability:
>      def parse_pcicaps(dir):
>          caps = []
>          has_extended_caps = False
> +        tlp_prefix_supported = False
>          f = input_open(os.path.join(dir, 'config'), 'rb')
>          f.seek(0x06)
>          (status,) = struct.unpack('<H', f.read(2))
> @@ -259,8 +260,6 @@ class PCICapability:
>                  (cap_reg,) = struct.unpack('<H', f.read(2))
>                  if (cap_reg & 0xf) >= 2:  # v2 capability
>                      len = 60
> -                # access side effects still need to be analyzed
> -                flags = PCICapability.RD

This leaves flags uninitialized for the Express case. What is the idea
behind this change?

>                  has_extended_caps = True
>              elif id == 0x11:  # MSI-X
>                  # access will be moderated by hypervisor
> @@ -297,6 +296,13 @@ class PCICapability:
>                      len = 64
>                      # access side effects still need to be analyzed
>                      flags = PCICapability.RD
> +                elif id == 0x0001:  # AER
> +                    if tlp_prefix_supported:
> +                        len = 0x48
> +                    else:
> +                        len = 0x38
> +                    # AER access is per-function
> +                    flags = PCICapability.RW
>                  else:
>                      if (id & PCICapability.JAILHOUSE_PCI_EXT_CAP) != 0:
>                          print('WARNING: Ignoring unsupported PCI Express '
> 

Minor, but this should be last, after core support is available.

Jan

-- 
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

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