pci_cfg_write_moderate() was changed to allow writes to the PCIe
capability, while Jailhouse will in fact only do reads and fake that
writes happen. This is getting in so that Linux thinks it did OK at
pci_disable_pcie_error_reporting() (disabling AER reporting for
functions will be taken care of at hypervisor level on following
patches). That is a common function call from .remove() struct
pci_driver entries on drivers. The register that is accessed there is
Device Control (offset 08h) or its bits enabling/disabling AER reporting
on a device.
This is a preparation for a scheme where Jailhouse will suppress all AER
reporting on device handover.
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.cha...@intel.com>
---
hypervisor/include/jailhouse/pci.h | 1 +
hypervisor/pci.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/hypervisor/include/jailhouse/pci.h
b/hypervisor/include/jailhouse/pci.h
index c0c10e96..720ecacd 100644
--- a/hypervisor/include/jailhouse/pci.h
+++ b/hypervisor/include/jailhouse/pci.h
@@ -37,6 +37,7 @@
#define PCI_CAP_MSI 0x05
#define PCI_CAP_MSIX 0x11
+#define PCI_CAP_EXPRESS 0x10
#define PCI_IVSHMEM_NUM_MMIO_REGIONS 2
diff --git a/hypervisor/pci.c b/hypervisor/pci.c
index 2f95dd74..60d877fc 100644
--- a/hypervisor/pci.c
+++ b/hypervisor/pci.c
@@ -350,6 +350,14 @@ enum pci_access pci_cfg_write_moderate(struct pci_device
*device, u16 address,
if (pci_update_msix(device, cap) < 0)
return PCI_ACCESS_REJECT;
+ /*
+ * Let guests think they did OK when writing to this
+ * capability. The register of interest in writes there is
+ * Device Control, but it affects things that Jailhouse will
+ * take care of at hypervisor level.
+ */
+ } else if (cap->id == PCI_CAP_EXPRESS) {
+ return PCI_ACCESS_DONE;
}
return PCI_ACCESS_PERFORM;
--
2.14.3
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