From: Jan von Wiarda <jan.vonwia...@emtrion.de>
This patchset removes the warnings of the latest 4.15 device tree compiler.
In addition it includes the defines of missing header files directly in the
device tree source file.
Signed-off-by: Jan von Wiarda <jan.vonwia...@emtrion.de>
Signed-off-by: Ruediger Fichter <ruediger.fich...@emtrion.de>
---
configs/arm/dts/inmate-emtrion-emconrzg1e.dts | 23 +++++++----------------
configs/arm/dts/inmate-emtrion-emconrzg1m.dts | 24 +++++++-----------------
2 files changed, 14 insertions(+), 33 deletions(-)
diff --git a/configs/arm/dts/inmate-emtrion-emconrzg1e.dts
b/configs/arm/dts/inmate-emtrion-emconrzg1e.dts
index 44266251..d04bd3e7 100644
--- a/configs/arm/dts/inmate-emtrion-emconrzg1e.dts
+++ b/configs/arm/dts/inmate-emtrion-emconrzg1e.dts
@@ -14,7 +14,9 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a7745-sysc.h>
+
+#define R8A7745_PD_CA7_CPU1 6
+#define R8A7745_PD_ALWAYS_ON 32
/dts-v1/;
@@ -37,18 +39,13 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu@1 {
enable-method = "psci";
device_type = "cpu";
compatible = "arm,cortex-a7";
- reg = <0x0>;
- clock-frequency = <0x3b9aca00>;
- power-domains = <0x2 0x5>;
- clocks = <0x3>;
- operating-points = <0xf4240 0xf4240>;
- next-level-cache = <0x4>;
- linux,phandle = <0x5>;
- phandle = <0x5>;
+ reg = <1>;
+ clock-frequency = <1000000000>;
+ power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
};
};
@@ -116,15 +113,10 @@
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7745";
reg = <0x0 0xe6060000 0x0 0x11c>;
- #gpio-range-cells = <0x3>;
- linux,phandle = <0x7>;
- phandle = <0x7>;
serial4 {
renesas,groups = "scif4_data_c";
renesas,function = "scif4";
- linux,phandle = <0x12>;
- phandle = <0x12>;
};
sdhi0_pins: sd0 {
@@ -163,7 +155,6 @@
status = "okay";
clocks = <&scif4_clk 0>;
clock-names = "peripheral_clk";
- pinctrl-0 = <0x12>;
pinctrl-names = "default";
};
diff --git a/configs/arm/dts/inmate-emtrion-emconrzg1m.dts
b/configs/arm/dts/inmate-emtrion-emconrzg1m.dts
index ee433010..d95a03d2 100644
--- a/configs/arm/dts/inmate-emtrion-emconrzg1m.dts
+++ b/configs/arm/dts/inmate-emtrion-emconrzg1m.dts
@@ -14,7 +14,9 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/r8a7743-sysc.h>
+
+#define R8A7743_PD_CA15_CPU1 1
+#define R8A7743_PD_ALWAYS_ON 32
/dts-v1/;
@@ -37,19 +39,13 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu@1 {
enable-method = "psci";
device_type = "cpu";
compatible = "arm,cortex-a15";
- reg = <0x0>;
- clock-frequency = <0x59682f00>;
- voltage-tolerance = <0x1>;
- clocks = <0x2 0x8>;
- clock-latency = <0x493e0>;
- power-domains = <0x3 0x0>;
- operating-points = <0x16e360 0xf4240 0x1406f4 0xf4240
- 0x112a88 0xf4240 0xe4e1c 0xf4240
- 0xb71b0 0xf4240 0x5b8d8 0xf4240>;
+ reg = <1>;
+ clock-frequency = <1500000000>;
+ power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
};
};
@@ -117,15 +113,10 @@
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7743";
reg = <0x0 0xe6060000 0x0 0x11c>;
- #gpio-range-cells = <0x3>;
- linux,phandle = <0x7>;
- phandle = <0x7>;
serial6 {
renesas,groups = "scif4_data_c";
renesas,function = "scif4";
- linux,phandle = <0x12>;
- phandle = <0x12>;
};
sdhi0_pins: sd0 {
@@ -164,7 +155,6 @@
status = "okay";
clocks = <&scif4_clk 0>;
clock-names = "peripheral_clk";
- pinctrl-0 = <0x12>;
pinctrl-names = "default";
};
--
2.11.0
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