On 2018-02-13 08:59, bharat gohil wrote:
> 
> 
> On Tue, Feb 13, 2018 at 12:58 PM, Jan Kiszka <jan.kis...@siemens.com
> <mailto:jan.kis...@siemens.com>> wrote:
> 
>     On 2018-02-13 08:19, bharat gohil wrote:
>     > Hi Jan,
>     >
>     > I tried your second method to bringdown core and check but result are 
> same,
>     >
>     > #cat /proc/cpuinfo
>     > processor       : 0
>     > BogoMIPS        : 26.00
>     > Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32
>     > CPU implementer : 0x41
>     > CPU architecture: 8
>     > CPU variant     : 0x0
>     > CPU part        : 0xd04
>     > CPU revision    : 1
>     >
>     > #jailhouse enable XXXXX.cell
>     >
>     > Initializing Jailhouse hypervisor v0.8 (9-g5eec601-dirty) on CPU 0
>     > Code location: 0x0000ffffc0200060
>     > Page pool usage after early setup: mem 57/16356, remap 16/131072
>     > Initializing processors:
>     >  CPU 0... OK
>     > Adding virtual PCI device 00:00.0 to cell "XXXXX"
>     > Page pool usage after late setup: mem 62/16356, remap 21/131072
>     > Activating hypervisor
> 
>     A lock-up, no more invalid access reports?
> 
>    There is no output and system hangs after "Activating hypervisor"
> 
> 
>     What is core 0? What are cores 1 and 2? What happens when you use those
>     cores only?
> 
>   Core 0 = A35
>   Core 1 = A35
>   Core 2 = A72
>   In above output i had bringdown Core 1(A35) and Core 2(A72) and Core
> 0(A35) is online and i have modified root cell config to  .cpus = {
> 0x1,} which Core 0(A35),
> 

I see. I suppose the A72 will not behave differently, but I would
quickly check that as well.

> 
>     Make sure to analyze the issue systematically. We see a problem now that
>     has a non-obvious cause.
> 
>    Yes.agree.
>    To bringup Xen on this platform, I had done some modification in Xen.
> Let me debug issue in this context as well.
> 

Good to know, then there is hope.

My current understanding of the situation is:
- we get an IABT on executing the first guest instruction after enabling
  Jailhouse
- that IABT means "page fault during stage-2 translation"
- the page table is created to contain 1:1 mapping for the faulting
  address to RAM with read/write/execute permissions

And that may mean:
- the CPU does not like the page table entry for some reason
- the CPU has a problem with the page table hierarchy format in general
- the root pointer is not correct when entering EL1
- there are other reasons that stage-2 faults that could cause this
  abort (would contradict the ARM manual in my eyes)

Jan

-- 
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

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