On 2018-03-06 18:43, Adeel Ahmad wrote:
> The bit field extractions are made more readable by the use
> of GET_FIELD macro, this also allows them to be mapped
> directly to processor manuals. This commit also
> includes a typo fix.
> 
> Signed-off-by: Adeel Ahmad <adeelahma...@hotmail.com>
> ---
>  hypervisor/arch/arm/include/asm/sysregs.h   | 10 ++++------
>  hypervisor/arch/arm64/include/asm/sysregs.h | 10 ++++------
>  2 files changed, 8 insertions(+), 12 deletions(-)
> 
> diff --git a/hypervisor/arch/arm/include/asm/sysregs.h 
> b/hypervisor/arch/arm/include/asm/sysregs.h
> index 6c9a53c..fb6b503 100644
> --- a/hypervisor/arch/arm/include/asm/sysregs.h
> +++ b/hypervisor/arch/arm/include/asm/sysregs.h
> @@ -107,13 +107,11 @@
>  #define ESR_EL2              SYSREG_32(4, c5, c2, 0)
>  #define HSR          ESR_EL2 /* AArch32 name */
>  /* exception class */
> -#define  HSR_EC_SHIFT                26
> -#define  HSR_EC(hsr)         ((hsr) >> HSR_EC_SHIFT & 0x3f)
> +#define  HSR_EC(esr)         GET_FIELD((esr), 31, 26)
>  /* instruction length */
> -#define  HSR_IL_SHIFT                25
> -#define  HSR_IL(hsr)         ((hsr) >> HSR_IL_SHIFT & 0x1)
> -/* Instruction specific */
> -#define  HSR_ISS(hsr)                ((hsr) & BIT_MASK(24, 0))
> +#define  HSR_IL(esr)         GET_FIELD((esr), 25, 25)
> +/* Instruction specific syndrome */
> +#define  HSR_ISS(esr)                GET_FIELD((esr), 24, 0)
>  /* Exception classes values */
>  #define  HSR_EC_UNK          0x00
>  #define  HSR_EC_WFI          0x01
> diff --git a/hypervisor/arch/arm64/include/asm/sysregs.h 
> b/hypervisor/arch/arm64/include/asm/sysregs.h
> index d3feee0..70c0d13 100644
> --- a/hypervisor/arch/arm64/include/asm/sysregs.h
> +++ b/hypervisor/arch/arm64/include/asm/sysregs.h
> @@ -107,13 +107,11 @@
>  #define HCR_VM_BIT   (1u << 0)
>  
>  /* exception class */
> -#define ESR_EC_SHIFT         26
> -#define ESR_EC(hsr)          ((hsr) >> ESR_EC_SHIFT & 0x3f)
> +#define ESR_EC(esr)          GET_FIELD((esr), 31, 26)
>  /* instruction length */
> -#define ESR_IL_SHIFT         25
> -#define ESR_IL(hsr)          ((hsr) >> ESR_IL_SHIFT & 0x1)
> -/* Instruction specific syndrom */
> -#define ESR_ISS(esr)         ((esr) & BIT_MASK(24, 0))
> +#define ESR_IL(esr)          GET_FIELD((esr), 25, 25)
> +/* Instruction specific syndrome */
> +#define ESR_ISS(esr)         GET_FIELD((esr), 24, 0)
>  /* Exception classes values */
>  #define ESR_EC_UNKNOWN               0x00
>  #define ESR_EC_WFx           0x01
> 

Applied to next.

Did you look around in other hypervisor files where shifting/masking
happens if this pattern applies there as well?

Thanks,
Jan
-- 
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux

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