Signed-off-by: Claudio Scordino <clau...@evidence.eu.com>
---
configs/arm64/jetson-tx2.c | 492 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 492 insertions(+)
create mode 100644 configs/arm64/jetson-tx2.c
diff --git a/configs/arm64/jetson-tx2.c b/configs/arm64/jetson-tx2.c
new file mode 100644
index 0000000..0d23158
--- /dev/null
+++ b/configs/arm64/jetson-tx2.c
@@ -0,0 +1,492 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for Jailhouse Jetson TX2 board
+ *
+ * Copyright (C) 2018 Evidence Srl
+ *
+ * Authors:
+ * Claudio Scordino <clau...@evidence.eu.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ * NOTE: Add "mem=7808M vmalloc=512M" to the kernel command line.
+ *
+ * 2:7000:0000 inmate (size: 100:0000 = 16 MB)
+ * 2:7100:0000 hypervisor (size: 400:0000 = 64 MB)
+ *
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[57];
+ struct jailhouse_irqchip irqchips[2];
+} __attribute__((packed)) config = {
+ .header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .hypervisor_memory = {
+ .phys_start = 0x271000000,
+ .size = 0x4000000,
+ },
+ .debug_console = {
+ .address = 0x3100000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_CON1_TYPE_8250 |
+ JAILHOUSE_CON1_ACCESS_MMIO |
+ JAILHOUSE_CON1_REGDIST_4 |
+ JAILHOUSE_CON2_TYPE_ROOTPAGE,
+ },
+ .platform_info = {
+
+ .arm = {
+ .gicd_base = 0x03881000,
+ .gicc_base = 0x03882000,
+ .gich_base = 0x03884000,
+ .gicv_base = 0x03886000,
+ .gic_version = 2,
+ .maintenance_irq = 25,
+ }
+ },
+ .root_cell = {
+ .name = "Jetson-TX2",
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ },
+ },
+
+ .cpus = {
+ 0x39,
+ },
+
+
+ .mem_regions = {
+ /* BPMP_ATCM */ {
+ .phys_start = 0x00000000,
+ .virt_start = 0x00000000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+
+ /* MISC */ {
+ .phys_start = 0x00100000,
+ .virt_start = 0x00100000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+
+ /* AXIP2P */ {
+ .phys_start = 0x02100000,
+ .virt_start = 0x02100000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* GPIO_CTL */ {
+ .phys_start = 0x02200000,
+ .virt_start = 0x02200000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* TSA */ {
+ .phys_start = 0x2400000,
+ .virt_start = 0x2400000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* PADCTL_A (PINMUX) */ {
+ .phys_start = 0x02430000,
+ .virt_start = 0x02430000,
+ .size = 0x15000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* UFSHC */ {
+ .phys_start = 0x02450000,
+ .virt_start = 0x02450000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* ETHER_QOS */ {
+ .phys_start = 0x02490000,
+ .virt_start = 0x02490000,
+ .size = 0x50000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* GPCDMA */ {
+ .phys_start = 0x02600000,
+ .virt_start = 0x02600000,
+ .size = 0x210000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* APE */ {
+ .phys_start = 0x02900000,
+ .virt_start = 0x02900000,
+ .size = 0x200000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* MSS */ {
+ .phys_start = 0x02c00000,
+ .virt_start = 0x02c00000,
+ .size = 0xb0000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* LIC */ {
+ .phys_start = 0x03000000,
+ .virt_start = 0x03000000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* TOP_TKE */ {
+ .phys_start = 0x03010000,
+ .virt_start = 0x03010000,
+ .size = 0xe0000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* TIMER */ {
+ .phys_start = 0x03020000,
+ .virt_start = 0x03020000,
+ .size = 0xa0000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* UARTA */ {
+ .phys_start = 0x03100000,
+ .virt_start = 0x03100000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* UART-B */ {
+ .phys_start = 0x03110000,
+ .virt_start = 0x03110000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* I2C */ {
+ .phys_start = 0x03160000,
+ .virt_start = 0x03160000,
+ .size = 0x90000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* PWM1 + PWM2 */ {
+ .phys_start = 0x03280000,
+ .virt_start = 0x03280000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* PWM3 - PWM8 */ {
+ .phys_start = 0x032a0000,
+ .virt_start = 0x032a0000,
+ .size = 0x60000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* SDMMC */ {
+ .phys_start = 0x3400000,
+ .virt_start = 0x3400000,
+ .size = 0x80000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* SATA */ {
+ .phys_start = 0x3500000,
+ .virt_start = 0x3500000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* HDA */ {
+ .phys_start = 0x3510000,
+ .virt_start = 0x3510000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* XUSB_PADCTL + XUSB_HOST */ {
+ .phys_start = 0x3520000,
+ .virt_start = 0x3520000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* XUSB */ {
+ .phys_start = 0x03540000,
+ .virt_start = 0x03540000,
+ .size = 0x20000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* FUSE + KFUSE */ {
+ .phys_start = 0x03820000,
+ .virt_start = 0x03820000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* MIPICAL */ {
+ .phys_start = 0x03990000,
+ .virt_start = 0x03990000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* TACH_0 */ {
+ .phys_start = 0x039c0000,
+ .virt_start = 0x039c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* SE0 */ {
+ .phys_start = 0x03ac0000,
+ .virt_start = 0x03ac0000,
+ .size = 0x30000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* TOP0_HSP */{
+ .phys_start = 0x03c00000,
+ .virt_start = 0x03c00000,
+ .size = 0xa0000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* CSITE */ {
+ .phys_start = 0x08000000,
+ .virt_start = 0x08000000,
+ .size = 0x2000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* SCE_PM */ {
+ .phys_start = 0x0b1f0000,
+ .virt_start = 0x0b1f0000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* SCE_CFG */ {
+ .phys_start = 0x0b230000,
+ .virt_start = 0x0b230000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* More I2C + SPI */ {
+ .phys_start = 0x0c230000,
+ .virt_start = 0x0c230000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* UARTC, UARTG, RTC, TSC */ {
+ .phys_start = 0x0c280000,
+ .virt_start = 0x0c280000,
+ .size = 0x70000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* AON_GPIO_0 */ {
+ .phys_start = 0x0c2f0000,
+ .virt_start = 0x0c2f0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* AON_PADCTL_0 (PINMUX) */ {
+ .phys_start = 0x0c300000,
+ .virt_start = 0x0c300000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* PMC */ {
+ .phys_start = 0x0c360000,
+ .virt_start = 0x0c360000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* ACTMON + SIMON + SOC_THERM */ {
+ .phys_start = 0x0d230000,
+ .virt_start = 0x0d230000,
+ .size = 0x70000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /*CCPLEX CLUSTER*/{
+ .phys_start = 0x0e000000,
+ .virt_start = 0x0e000000,
+ .size = 0x400000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* PCIE0 */ {
+ .phys_start = 0x10000000,
+ .virt_start = 0x10000000,
+ .size = 0x1000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* SMMU0 */ {
+ .phys_start = 0x12000000,
+ .virt_start = 0x12000000,
+ .size = 0x1000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* HOST1X */ {
+ .phys_start = 0x13e00000,
+ .virt_start = 0x13e00000,
+ .size = 0x90000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* HOST1X_ACTMON */ {
+ .phys_start = 0x13ec0000,
+ .virt_start = 0x13ec0000,
+ .size = 0x50000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* DPAUX1 */ {
+ .phys_start = 0x15040000,
+ .virt_start = 0x15040000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* NVCSI */ {
+ .phys_start = 0x150c0000,
+ .virt_start = 0x150c0000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* TSECB */ {
+ .phys_start = 0x15100000,
+ .virt_start = 0x15100000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* NVDISPLAY */ {
+ .phys_start = 0x15200000,
+ .virt_start = 0x15200000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* VIC */ {
+ .phys_start = 0x15340000,
+ .virt_start = 0x15340000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* NVJPG */ {
+ .phys_start = 0x15380000,
+ .virt_start = 0x15380000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* NVDEC + NVENC + TSEC + ISP + SOR */ {
+ .phys_start = 0x15480000,
+ .virt_start = 0x15480000,
+ .size = 0x1c0000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* NI */ {
+ .phys_start = 0x15700000,
+ .virt_start = 0x15700000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* SE1-SE4 */ {
+ .phys_start = 0x15810000,
+ .virt_start = 0x15810000,
+ .size = 0x40000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* GPU */ {
+ .phys_start = 0x17000000,
+ .virt_start = 0x17000000,
+ .size = 0x9000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* SYSRAM_0 */{
+ .phys_start = 0x30000000,
+ .virt_start = 0x30000000,
+ .size = 0x10000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+
+ /* System RAM */ {
+ .phys_start = 0x80000000,
+ .virt_start = 0x80000000,
+ .size = 0x1F0000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* Inmate */ {
+ .phys_start = 0x270000000,
+ .virt_start = 0x270000000,
+ .size = 0x1000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* Persistent RAM */ {
+ .phys_start = 0x277080000,
+ .virt_start = 0x277080000,
+ .size = 0x200000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ },
+ .irqchips = {
+ /* GIC */ {
+ .address = 0x03881000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
+ },
+ },
+ /* GIC */ {
+ .address = 0x03881000,
+ .pin_base = 160,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff
+ },
+ },
+ },
+
+};
--
2.7.4
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