On 30.09.18 22:55, Ralf Ramsauer wrote:
On 9/30/18 8:39 PM, Jan Kiszka wrote:
From: Jan Kiszka <[email protected]>
Add configs for the Marvell Armada 8040-based MACCHIATObin board. MSI
support should eventually be possible as well, but we still with INTx
for the virtual shmem devices for now.
Signed-off-by: Jan Kiszka <[email protected]>
---
Changes in v2:
- fix UART type in linux-demo
- fix overlong line
configs/arm64/dts/inmate-macchiatobin.dts | 106 +++++++++++++++++++++++
configs/arm64/macchiatobin-gic-demo.c | 72 ++++++++++++++++
configs/arm64/macchiatobin-linux-demo.c | 124 +++++++++++++++++++++++++++
configs/arm64/macchiatobin.c | 134 ++++++++++++++++++++++++++++++
4 files changed, 436 insertions(+)
create mode 100644 configs/arm64/dts/inmate-macchiatobin.dts
create mode 100644 configs/arm64/macchiatobin-gic-demo.c
create mode 100644 configs/arm64/macchiatobin-linux-demo.c
create mode 100644 configs/arm64/macchiatobin.c
diff --git a/configs/arm64/dts/inmate-macchiatobin.dts
b/configs/arm64/dts/inmate-macchiatobin.dts
new file mode 100644
index 00000000..3ac66b54
--- /dev/null
+++ b/configs/arm64/dts/inmate-macchiatobin.dts
@@ -0,0 +1,106 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Device tree for Linux inmate test on MACCHIATObin,
+ * corresponds to configs/arm64/macchiatobin-linux-demo.c
+ *
+ * Copyright (c) Siemens AG, 2016-2018
+ *
+ * Authors:
+ * Jan Kiszka <[email protected]>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+ model = "Jailhouse cell on MACCHIATObin";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ interrupt-parent = <&gic>;
+
+ hypervisor {
+ compatible = "jailhouse,cell";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@100 {
+ compatible = "arm,cortex-a72", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+ cpu@101 {
+ compatible = "arm,cortex-a72", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x101>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ gic: interrupt-controller@f0210000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0xf0210000 0x0 0x10000>, /* GICD */
+ <0x0 0xf022f000 0x0 0x20000>; /* GICC */
+ };
+
+ ap_syscon: system-controller@6f4000 {
Is there a reason why you leave out the f0?
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0xf06f4000 0 0x2000>;
+
+ ap_clk: clock {
+ compatible = "marvell,ap806-clock";
+ #clock-cells = <1>;
+ };
+ };
+
+ uart0: serial@512000 {
Same here, shouldn't this be f0512000?
Copy&pasted from the original DTB where this is under the offset of an outer
node at f0000000. No semantical relevance, just names, but I can adjust that.
I'm also considering to set pci_domain and rely on a kernel patch to adjust the
board DTB accordingly, just like we already do for the ESPRESSObin. Gives stable
PCI addresses across disable/enable.
Jan
--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux
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