On 19.10.18 17:18, posk.de...@gmail.com wrote:
Hello!
GICv3 on ARM provides the ability to route interrupts to specific cores, see e.g.
"Affinity routing and assignment" here:
https://static.docs.arm.com/100336/0002/corelink_gic600_generic_interrupt_controller_technical_reference_manual_100336_0002_01_en.pdf
A paper on Jailhouse (https://arxiv.org/abs/1705.06932) measures interrupt
delays introduced by trapping them in hypervisor and re-injecting into
cells/VMs. Why can't GIC be programmed by the hypervisor to route interrupts
directly to CPUs controlled by a cell, thus eliminating the extra hop to the
hypervisor?
Only GICv4 introduces a way to inject a physical interrupt directly into the
virtual CPU. I'm sure we will eventually support that, but I'm not yet aware of
any physical hardware implementing GICv4 (GICv3 adoption is still "in process").
Jan
--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux
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