From: Andreas Messerschmid <andr...@linutronix.de>
Add a root cell configuration file for the Microsys
Miriac LS1046a SBC.
Signed-off-by: Andreas Messerschmid <andr...@linutronix.de>
Reviewed-by: Benedikt Spranger <b.spran...@linutronix.de>
---
configs/arm64/miriac-sbc-ls1046a.c | 458 +++++++++++++++++++++++++++++++++++++
1 file changed, 458 insertions(+)
create mode 100644 configs/arm64/miriac-sbc-ls1046a.c
diff --git a/configs/arm64/miriac-sbc-ls1046a.c
b/configs/arm64/miriac-sbc-ls1046a.c
new file mode 100644
index 00000000..a8fb5b4c
--- /dev/null
+++ b/configs/arm64/miriac-sbc-ls1046a.c
@@ -0,0 +1,458 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for Microsys miriac SBC-LS1046A board
+ *
+ * Copyright (c) Linutronix GmbH, 2019
+ *
+ * Authors:
+ * Andreas Messerschmid <andreas.messersch...@linutronix.de>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ *
+ * Reservation via device tree: 0xc0000000..0xffffffff
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[50];
+ struct jailhouse_irqchip irqchips[2];
+ struct jailhouse_pci_device pci_devices[1];
+} __attribute__((packed)) config = {
+ .header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory = {
+ .phys_start = 0xc0000000,
+ .size = 0x000400000,
+ },
+
+ .debug_console = {
+ .address = 0x021c0500,
+ .size = 0x100,
+ .type = JAILHOUSE_CON_TYPE_8250,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_1,
+ },
+
+ .platform_info = {
+ .pci_mmconfig_base = 0x13000000,
+ .pci_mmconfig_end_bus = 0,
+ .pci_is_virtual = 1,
+ .pci_domain = -1,
+ .arm = {
+ .gic_version = 2,
+ .gicd_base = 0x1410000,
+ .gicc_base = 0x142f000,
+ .gich_base = 0x1440000,
+ .gicv_base = 0x146f000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "miriac SBC-LS1046A",
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+
+ .vpci_irq_base = 102-32,
+ },
+ },
+
+ .cpus = {
+ 0xf,
+ },
+
+ .mem_regions = {
+ /* 0 - DDR memory controller */ {
+ .phys_start = 0x01080000,
+ .virt_start = 0x01080000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 1 - IFC */ {
+ .phys_start = 0x01530000,
+ .virt_start = 0x01530000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 2 - QSPI */ {
+ .phys_start = 0x01550000,
+ .virt_start = 0x01550000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 3 - esdhc */ {
+ .phys_start = 0x01560000,
+ .virt_start = 0x01560000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 4 - scfg */ {
+ .phys_start = 0x01570000,
+ .virt_start = 0x01570000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 5 - crypto */ {
+ .phys_start = 0x01700000,
+ .virt_start = 0x01700000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 6 - qman */ {
+ .phys_start = 0x01880000,
+ .virt_start = 0x01880000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 7 - bman */ {
+ .phys_start = 0x01890000,
+ .virt_start = 0x01890000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 8 - fman */ {
+ .phys_start = 0x01a00000,
+ .virt_start = 0x01a00000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 9 - qportals */ {
+ .phys_start = 0x500000000,
+ .virt_start = 0x500000000,
+ .size = 0x8000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 10 - bportals */ {
+ .phys_start = 0x508000000,
+ .virt_start = 0x508000000,
+ .size = 0x8000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 11 - dcfg */ {
+ .phys_start = 0x01ee0000,
+ .virt_start = 0x01ee0000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 12 - clockgen */ {
+ .phys_start = 0x01ee1000,
+ .virt_start = 0x01ee1000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 13 - rcpm */ {
+ .phys_start = 0x01ee2000,
+ .virt_start = 0x01ee2000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 14 - tmu */ {
+ .phys_start = 0x01f00000,
+ .virt_start = 0x01f00000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 15 - dspi */ {
+ .phys_start = 0x02100000,
+ .virt_start = 0x02100000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 16 - i2c0 */ {
+ .phys_start = 0x02180000,
+ .virt_start = 0x02180000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 17 - i2c1 */ {
+ .phys_start = 0x02190000,
+ .virt_start = 0x02190000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 18 - i2c2 */ {
+ .phys_start = 0x021a0000,
+ .virt_start = 0x021a0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 19 - i2c3 */ {
+ .phys_start = 0x021b0000,
+ .virt_start = 0x021b0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 20 - duart1 */ {
+ .phys_start = 0x021c0000,
+ .virt_start = 0x021c0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 21 - duart2 */ {
+ .phys_start = 0x021d0000,
+ .virt_start = 0x021d0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 22 - gpio0 */ {
+ .phys_start = 0x02300000,
+ .virt_start = 0x02300000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 23 - gpio1 */ {
+ .phys_start = 0x02310000,
+ .virt_start = 0x02310000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 24 - gpio2 */ {
+ .phys_start = 0x02320000,
+ .virt_start = 0x02320000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 25 - gpio3 */ {
+ .phys_start = 0x02330000,
+ .virt_start = 0x02330000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 26 - lpuart0 */ {
+ .phys_start = 0x02950000,
+ .virt_start = 0x02950000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 27 - lpuart1 */ {
+ .phys_start = 0x02960000,
+ .virt_start = 0x02960000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 28 - lpuart2 */ {
+ .phys_start = 0x02970000,
+ .virt_start = 0x02970000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 29 - lpuart3 */ {
+ .phys_start = 0x02980000,
+ .virt_start = 0x02980000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 30 - lpuart4 */ {
+ .phys_start = 0x02990000,
+ .virt_start = 0x02990000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 31 - lpuart5 */ {
+ .phys_start = 0x029a0000,
+ .virt_start = 0x029a0000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 32 - wdog0 */ {
+ .phys_start = 0x02ad0000,
+ .virt_start = 0x02ad0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 33 - edma0 */ {
+ .phys_start = 0x02c00000,
+ .virt_start = 0x02c00000,
+ .size = 0x30000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 34 - usb0 */ {
+ .phys_start = 0x02f00000,
+ .virt_start = 0x02f00000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 35 - usb1 */ {
+ .phys_start = 0x03000000,
+ .virt_start = 0x03000000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 36 - usb2 */ {
+ .phys_start = 0x03100000,
+ .virt_start = 0x03100000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 37 - sata */ {
+ .phys_start = 0x03200000,
+ .virt_start = 0x03200000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 38 - msi1 */ {
+ .phys_start = 0x01580000,
+ .virt_start = 0x01580000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 39 - msi2 */ {
+ .phys_start = 0x01590000,
+ .virt_start = 0x01590000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 40 - msi3 */ {
+ .phys_start = 0x015a0000,
+ .virt_start = 0x015a0000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 41 - pcie0 */ {
+ .phys_start = 0x03400000,
+ .virt_start = 0x03400000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 42 - pcie1 */ {
+ .phys_start = 0x03500000,
+ .virt_start = 0x03500000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 43 - pcie2 */ {
+ .phys_start = 0x03600000,
+ .virt_start = 0x03600000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 44 - RAM - 1GB - root cell */ {
+ .phys_start = 0x80000000,
+ .virt_start = 0x80000000,
+ .size = 0x40000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* 45 - RAM - ~1GB - inmates */ {
+ .phys_start = 0xc0500000,
+ .virt_start = 0xc0500000,
+ .size = 0x3fb00000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* 46 - IVSHMEM shared memory region for 00:00.0 */ {
+ .phys_start = 0xc0400000,
+ .virt_start = 0xc0400000,
+ .size = 0x100000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* 47 - PCI host bridge 0 */ {
+ .phys_start = 0x4000000000,
+ .virt_start = 0x4000000000,
+ .size = 0x800000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 48 - PCI host bridge 1 */ {
+ .phys_start = 0x4800000000,
+ .virt_start = 0x4800000000,
+ .size = 0x800000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* 49 - PCI host bridge 2 */ {
+ .phys_start = 0x5000000000,
+ .virt_start = 0x5000000000,
+ .size = 0x800000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ },
+
+ .irqchips = {
+ /* GIC */ {
+ .address = 0x1410000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ /* GIC */ {
+ .address = 0x1410000,
+ .pin_base = 160,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ },
+
+ .pci_devices = {
+ /* 0000:00:00.0 */ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 1,
+ .bdf = 0 << 3,
+ .bar_mask = {
+ 0xffffff00, 0xffffffff, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000,
+ },
+ .shmem_region = 46,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
+ },
+ },
+};
--
2.11.0
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