> -----Original Message-----
> From: Andreas Schwab [mailto:[email protected]]
> Sent: 2019年2月13日 21:59
> To: Peng Fan <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; Catalin Marinas
> <[email protected]>
> Subject: Re: Warning: unpredictable: identical transfer and status registers
> --`stxr w4,x5,[x4] using aarch64 poky gcc 8.3
>
> On Feb 13 2019, Peng Fan <[email protected]> wrote:
>
> > static inline int test_and_set_bit(int nr, volatile unsigned long
> > *addr) {
> > u32 ret;
> > u64 test, tmp;
> >
> > BITOPT_ALIGN(nr, addr);
> >
> > /* AARCH64_TODO: using Inner Shareable DMB at the moment,
> > * revisit when we will deal with shareability domains */
> >
> > do {
> > asm volatile (
> > "ldxr %3, %2\n\t"
> > "ands %1, %3, %4\n\t"
> > "b.ne 1f\n\t"
> > "orr %3, %3, %4\n\t"
> > "1:\n\t"
> > "stxr %w0, %3, %2\n\t"
> > "dmb ish\n\t"
> > : "=r" (ret), "=&r" (test),
> > "+Q" (*(volatile unsigned long *)addr),
> > "=r" (tmp)
> > : "r" (1ul << nr));
>
> %3 is modified early, but not marked earlyclobber.
Thanks, I'll try add earlyclobber.
Peng
>
> Andreas.
>
> --
> Andreas Schwab, SUSE Labs, [email protected] GPG Key fingerprint = 0196
> BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something
> completely different."
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