Branch: refs/heads/coverity_scan
Home: https://github.com/siemens/jailhouse
Commit: 2b9a200d6dbacccc3d58113ec26e003d24f52dc2
https://github.com/siemens/jailhouse/commit/2b9a200d6dbacccc3d58113ec26e003d24f52dc2
Author: Peng Fan <[email protected]>
Date: 2019-02-15 (Fri, 15 Feb 2019)
Changed paths:
M hypervisor/arch/arm64/include/asm/bitops.h
Log Message:
-----------
arm64: bitops: fix test_and_set_bit
When compiling code using aarch64 poky gcc 8.2, met the warning:
"
CC hypervisor/printk.o
/tmp/cclKpFV2.s: Assembler messages:
/tmp/cclKpFV2.s:1306: Warning: unpredictable: identical transfer and status
registers --`stxr w4,x5,[x4]'
"
According to DDI0487D_a_armv8_arm, section "C6.2.285 STXR",
"
if s == n && n != 31 then
Constraint c = ConstrainUnpredictable();
assert c IN {Constraint_UNKNOWN, Constraint_NONE, Constraint_UNDEF,
Constraint_NOP};
case c of
when Constraint_UNKNOWN rn_unknown = TRUE; // address is UNKNOWN
when Constraint_NONE rn_unknown = FALSE; // address is original base
when Constraint_UNDEF UNDEFINED;
when Constraint_NOP EndOfInstruction();
"
And ConstrainUnpredictable means:
"
shared/functions/unpredictable/ConstrainUnpredictable
// Return the appropriate Constraint result to control the caller's behavior.
The return value
// is IMPLEMENTATION DEFINED within a permitted list for each UNPREDICTABLE
case.
// (The permitted list is determined by an assert or case statement at the call
site.)
"
So we need to avoid the situation that s == n returns true.
Without this patch, the asm code as following in panic_prink
ffffc0207ac0: 91006024 add x4, x1, #0x18
ffffc0207ac4: c85f7c85 ldxr x5, [x4]
ffffc0207ac8: ea0200a3 ands x3, x5, x2
ffffc0207acc: 54000041 b.ne ffffc0207ad4
<panic_printk+0x40> // b.any
ffffc0207ad0: aa0200a5 orr x5, x5, x2
ffffc0207ad4: c8047c85 stxr w4, x5, [x4]
ffffc0207ad8: d5033bbf dmb ish
ffffc0207adc: 35ffff24 cbnz w4, ffffc0207ac0
<panic_printk+0x2c>
when read and write a register operand, we need to ensure that these
operands are annotated as "early clobber" if the register is written
before all of the input operands have been consumed. So need to add
early clobber for op3 to force it into a different register from op4.
Also need an early-clobber on op0 to force it into a different register
from op2 (which for purposes of register assignment is an input operand
holding an address).
With this patch, the asm code as following:
ffffc0207a0c: 91006026 add x6, x1, #0x18
ffffc0207a10: c85f7cc5 ldxr x5, [x6]
ffffc0207a14: ea0200a3 ands x3, x5, x2
ffffc0207a18: 54000041 b.ne ffffc0207a20
<panic_printk+0x40> // b.any
ffffc0207a1c: aa0200a5 orr x5, x5, x2
ffffc0207a20: c8047cc5 stxr w4, x5, [x6]
ffffc0207a24: d5033bbf dmb ish
ffffc0207a28: 35ffff24 cbnz w4, ffffc0207a0c
<panic_printk+0x2c>
mail: https://www.mail-archive.com/[email protected]/msg87351.html
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: f743631213a1f1e2cd007950b9b557501006260b
https://github.com/siemens/jailhouse/commit/f743631213a1f1e2cd007950b9b557501006260b
Author: Flynn Xu <[email protected]>
Date: 2019-02-21 (Thu, 21 Feb 2019)
Changed paths:
M driver/pci.c
Log Message:
-----------
driver: pci: Fix refcount leak
pci_get_domain_bus_and_slot will incease refcount of l_dev, there
should be a pci_dev_put(l_dev) to decrease the refcount, otherwise
the resource will not be free.
Signed-off-by: Flynn xu <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 98c83bd9bbdb389872f6c237211b01de8c33627c
https://github.com/siemens/jailhouse/commit/98c83bd9bbdb389872f6c237211b01de8c33627c
Author: Peng Fan <[email protected]>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hypervisor/arch/arm64/include/asm/sysregs.h
M hypervisor/arch/arm64/traps.c
Log Message:
-----------
arm64: correct macro name
Accessing sysreg need to use msr or mrs instructions, not mcr or mrc.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: dc88bcda0cfc0a3ef2d430fdea9bcddcb36da70d
https://github.com/siemens/jailhouse/commit/dc88bcda0cfc0a3ef2d430fdea9bcddcb36da70d
Author: [email protected] <[email protected]>
Date: 2019-03-24 (Sun, 24 Mar 2019)
Changed paths:
M tools/jailhouse-hardware-check
Log Message:
-----------
hardware check: Catch errors opening /dev/mem during MMIO check
Catch error, print, and continue, instead of exiting test.
Signed-off-by: Michael Hinton <[email protected]>
[Jan: avoid duplicate error message]
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 31829c1058255a70558f5e3ef6a96b02b0e65f0a
https://github.com/siemens/jailhouse/commit/31829c1058255a70558f5e3ef6a96b02b0e65f0a
Author: Ralf Ramsauer <[email protected]>
Date: 2019-03-24 (Sun, 24 Mar 2019)
Changed paths:
M hypervisor/arch/arm-common/smccc.c
Log Message:
-----------
arm-common: smccc: fix missing break statement
Without breaking the ARM_SMCCC_OWNER_ARCH case, we will fall through and
end up in the ARM_SMCCC_OWNER_SIP case which is clearly a mistake.
Fix this bug by adding the break statement for the ARM_SMCCC_OWNER_ARCH
case.
Fixes: 075879bd0d48 ("arm-common: crash cell on unhandled SMC traps")
Signed-off-by: Ralf Ramsauer <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Compare:
https://github.com/siemens/jailhouse/compare/58786d1a0843...31829c105825
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