Branch: refs/heads/wip/cache-coloring
Home: https://github.com/siemens/jailhouse
Commit: 914ee2709a94c44e7b407b375011545ec274d104
https://github.com/siemens/jailhouse/commit/914ee2709a94c44e7b407b375011545ec274d104
Author: Luca Miccio <[email protected]>
Date: 2019-06-14 (Fri, 14 Jun 2019)
Changed paths:
A include/jailhouse/coloring.h
Log Message:
-----------
Common: introduce cache coloring primitives
Add fundamental primitives to implement support for cache coloring,
available both from the driver and hypervisor modules.
Define two main functions:
- calculate which bit range in an address is useful for cache coloring,
assuming it limited by the page size and the LLC way size as happens on
Arm;
- calculate the next physical page address that conforms to a given colors
selection and to the bits calculated in the previous function.
Signed-off-by: Luca Miccio <[email protected]>
Signed-off-by: Marco Solieri <[email protected]>
Signed-off-by: Renato Mancuso <[email protected]>
Commit: f12e23fb27e5c4971cef50b8c8927899533d3607
https://github.com/siemens/jailhouse/commit/f12e23fb27e5c4971cef50b8c8927899533d3607
Author: Luca Miccio <[email protected]>
Date: 2019-06-14 (Fri, 14 Jun 2019)
Changed paths:
M hypervisor/arch/arm-common/mmu_cell.c
M hypervisor/control.c
M hypervisor/include/jailhouse/paging.h
M hypervisor/paging.c
M include/jailhouse/cell-config.h
Log Message:
-----------
Hypervisor: implement cache-colored paging for Arm
Add functions for colored page creation and destruction, and introduce
new memory flags to mark colored regions.
The story of the life of a coloring page can be summarized as follows.
1. Bits in the address that are useful for defining colors are computed, and
used for all mappings. The page size used to obtain the lower limit is
assumed to be aligned with the `PAGE_SIZE` constant defaulting at 4 KiB,
and also as the unit for the mapping operation, even when consecutive pages
would be possible.
2. The colored regions can then mapped with a new paging function and
destructed with the old one, because `paging_destroy*` acts on virtual
addresses and while coloring happens on the physical ones.
3. The colored unmap function is instead used only when destroying the root
cell mapping, since we assume that the root cell uses a 1:1 mapping for
memory regions.
Signed-off-by: Luca Miccio <[email protected]>
Signed-off-by: Marco Solieri <[email protected]>
Commit: 1b5d2ed0e427833ffd103c7283c1e3bd0b977f01
https://github.com/siemens/jailhouse/commit/1b5d2ed0e427833ffd103c7283c1e3bd0b977f01
Author: Luca Miccio <[email protected]>
Date: 2019-06-14 (Fri, 14 Jun 2019)
Changed paths:
M hypervisor/control.c
M include/jailhouse/hypercall.h
Log Message:
-----------
Hypervisor: add hypercall to ease loading of cache-colored images
Add a new hypercall that maps a colored memory region to the root cell so
that it can be seen as a contiguous region. This allows the usual load
function in the Jailhouse driver to be seamlessly used; it also avoid
duplicating the coloring logic by keeping it all in the hypervisor.
Signed-off-by: Luca Miccio <[email protected]>
Signed-off-by: Marco Solieri <[email protected]>
Commit: 865c37a86b393484ac12660c09153d4ac7cdd1a4
https://github.com/siemens/jailhouse/commit/865c37a86b393484ac12660c09153d4ac7cdd1a4
Author: Luca Miccio <[email protected]>
Date: 2019-06-14 (Fri, 14 Jun 2019)
Changed paths:
M driver/Makefile
M driver/cell.c
A driver/coloring.c
A driver/coloring.h
M driver/main.c
Log Message:
-----------
Driver: add support for cache-colored memory configurations
Add support for colored memory region in Jailhouse driver module and
implement an automatic colored allocation system.
The hypervisor module implements the coloring logic and it can be used
by defining appropriate memory regions inside inmates configurations.
Add a new set of functions in order to create a more controlled cell
creation process if coloring is activated.
We support two types of coloring configuration:
- manual: the user must take care of all coloring problems (e.g. memory
overlapping, real size used and so on);
- automatic: the user has to define only the colors for the region and
the driver interface will take care of everything, assuming to assign
portions of a unique colored memory region and showing up errors if
needed.
N.B. The coloring interface is enabled in the Makefile only for Arm v8
because it is the only architecture tested.
Signed-off-by: Luca Miccio <[email protected]>
Signed-off-by: Marco Solieri <[email protected]>
Commit: 3b71560b4620dff81357d569d2db45630dabd9ec
https://github.com/siemens/jailhouse/commit/3b71560b4620dff81357d569d2db45630dabd9ec
Author: Luca Miccio <[email protected]>
Date: 2019-06-14 (Fri, 14 Jun 2019)
Changed paths:
M tools/jailhouse-cell-linux
Log Message:
-----------
Support cache-colored memory configurations when loading Linux inmate
Since cache coloring support adds a parameter (colors selection) to the
`jailhouse_memory` struct, update the script to allow Linux inmates
to be loaded.
Change the format accordingly to the modified struct and add the color
parameter also to the `MemoryRegion` class.
Signed-off-by: Luca Miccio <[email protected]>
Signed-off-by: Marco Solieri <[email protected]>
Commit: ab972798ea0ecc8596ca28bd2be2601807c39546
https://github.com/siemens/jailhouse/commit/ab972798ea0ecc8596ca28bd2be2601807c39546
Author: Luca Miccio <[email protected]>
Date: 2019-06-14 (Fri, 14 Jun 2019)
Changed paths:
A configs/arm64/zynqmp-zcu102-col.c
A configs/arm64/zynqmp-zcu102-demo-col.c
A configs/arm64/zynqmp-zcu102-linux-demo-col.c
Log Message:
-----------
Configs: zynqmp-zcu102: add cache-coloring examples
Add colored root cell configuration for the ZCU102 evaluation board
along with two non root-cell configurations both for a bare metal inmate
and for a Linux one. In these configurations we are using the automated
colored allocation and we are assigning to each memory regions half of
the available colors on the platform.
Signed-off-by: Luca Miccio <[email protected]>
Signed-off-by: Marco Solieri <[email protected]>
Commit: d56b3a0ea14fc4d1e057a0cb8f8aebd299c3365c
https://github.com/siemens/jailhouse/commit/d56b3a0ea14fc4d1e057a0cb8f8aebd299c3365c
Author: Luca Miccio <[email protected]>
Date: 2019-06-14 (Fri, 14 Jun 2019)
Changed paths:
A configs/arm64/jetson-tx2-col.c
A configs/arm64/jetson-tx2-demo-col.c
Log Message:
-----------
Configs: jetson-tx2: add cache-coloring examples
Add colored root cell configuration for the NVIDIA TX2 development board
along with an example of a non root-cell configuration for a bare metal inmate.
In these configurations we are using the automated colored allocation and we
are assigning to each memory regions half of the available colors on the
platform.
Signed-off-by: Luca Miccio <[email protected]>
Signed-off-by: Marco Solieri <[email protected]>
Commit: ef4ac0fc80a68132b639440905d415194979d90d
https://github.com/siemens/jailhouse/commit/ef4ac0fc80a68132b639440905d415194979d90d
Author: Luca Miccio <[email protected]>
Date: 2019-06-14 (Fri, 14 Jun 2019)
Changed paths:
A Documentation/cache-coloring.md
Log Message:
-----------
Documentation: add description and usage of cache coloring support
Signed-off-by: Luca Miccio <[email protected]>
Signed-off-by: Marco Solieri <[email protected]>
Compare:
https://github.com/siemens/jailhouse/compare/914ee2709a94%5E...ef4ac0fc80a6
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