Am Dienstag, 25. Juni 2019 15:27:41 UTC+2 schrieb Ralf Ramsauer:
> On 6/25/19 3:21 PM, Adam Przybylski wrote:
> > Am Dienstag, 25. Juni 2019 14:50:44 UTC+2 schrieb Ralf Ramsauer:
> >> On 6/25/19 2:46 PM, Adam Przybylski wrote:
> >>> Am Dienstag, 25. Juni 2019 14:14:41 UTC+2 schrieb Ralf Ramsauer:
> >>>> On 6/25/19 1:31 PM, Adam Przybylski wrote:
> >>>>> Am Dienstag, 25. Juni 2019 12:10:03 UTC+2 schrieb Ralf Ramsauer:
> >>>>>> Hi,
> >>>>>>
> >>>>>> On 6/25/19 9:38 AM, Adam Przybylski wrote:
> >>>>>>> Am Sonntag, 23. Juni 2019 18:32:37 UTC+2 schrieb Henning Schild:
> >>>>>>>> Am Fri, 21 Jun 2019 07:18:14 -0700
> >>>>>>>> schrieb Adam Przybylski:
> >>>>>>>>
> >>>>>>>>> Am Freitag, 21. Juni 2019 15:54:15 UTC+2 schrieb Henning Schild:
> >>>>>>>>>> Am Fri, 21 Jun 2019 14:51:30 +0200
> >>>>>>>>>> schrieb Ralf Ramsauer:
> >>>>>>>>>>
> >>>>>>>>>>> Hi,
> >>>>>>>>>>>
> >>>>>>>>>>> On 6/21/19 2:22 PM, Valentine Sinitsyn wrote:
> >>>>>>>>>>>> Hi Adam,
> >>>>>>>>>>>>
> >>>>>>>>>>>> On 21.06.2019 17:16, Adam Przybylski wrote:
> >>>>>>>>>>>>> Dear Jailhouse Community,
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> I am trying to enabled Jailhouse on the AMD EPYC 7351P 16-Core
> >>>>>>>>>>>>> Processor. Unfortunately the system hangs after I execute
> >>>>>>>>>>>>> "jailhouse enable sysconfig.cell".
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> Do you have any hint how to debug and instrument this issue?
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> Any kind of help is appreciated.
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> Attached you can find the jailhouse logs, processor info, and
> >>>>>>>>>>>>> sysconfig.c.
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> Looking forward to hear from you.
> >>>>>>>>>>>> I'd say the following line is the culprit:
> >>>>>>>>>>>>
> >>>>>>>>>>>>> FATAL: Invalid PIO read, port: 814 size: 1
> >>>>>>>>>>>
> >>>>>>>>>>> Could you please attach /proc/ioports? This will tell us the
> >>>>>>>>>>> secret behind Port 814.
> >>>>>>>>>>
> >>>>>>>>>> Not always, the driver doing that has to be so friendly to register
> >>>>>>>>>> the region.
> >>>>>>>>>>
> >>>>>>>>>>>>
> >>>>>>>>>>>> As a quick fix, you may grant your root cell access to all I/O
> >>>>>>>>>>>> ports and see if it helps.
> >>>>>>>>>>>
> >>>>>>>>>>> Allowing access will suppress the symptoms, yet we should
> >>>>>>>>>>> investigate its cause. Depending on the semantics of Port 819, to
> >>>>>>>>>>> allow access might have unintended side effects.
> >>>>>>>>>>>
> >>>>>>>>>>> You could also try to disassemble your kernel (objdump -d
> >>>>>>>>>>> vmlinux) and check what function hides behind the instruction
> >>>>>>>>>>> pointer at the moment of the crash 0xffffffffa4ac3114.
> >>>>>>>>>>
> >>>>>>>>>> A look in the System.map can also answer that question. On a distro
> >>>>>>>>>> that will be ready to read somewhere in /boot/.
> >>>>>>>>>>
> >>>>>>>>>> Henning
> >>>>>>>>>>
> >>>>>>>>>>> Ralf
> >>>>>>>>>>>
> >>>>>>>>>>>>
> >>>>>>>>>>>> Best,
> >>>>>>>>>>>> Valentine
> >>>>>>>>>>>>
> >>>>>>>>>>>>>
> >>>>>>>>>>>>> Kind regards,
> >>>>>>>>>>>>> Adam Przybylski
> >>>>>>>>>>>>>
> >>>>>>>>>>>>
> >>>>>>>>>>>
> >>>>>>>>>
> >>>>>>>>> Hi,
> >>>>>>>>>
> >>>>>>>>> I looked up the function which gets executed in the Kernel. It's
> >>>>>>>>> "acpi_idle_do_entry".
> >>>>>>>>
> >>>>>>>> Well now you are back to what Valentine said. Open up those ports one
> >>>>>>>> by one, until the problem goes away. The alternative is to disable
> >>>>>>>> the
> >>>>>>>> drivers in the root-linux. In the case of ACPI i.e. acpi=off as
> >>>>>>>> kernel
> >>>>>>>> parameter, but you probably do not want that.
> >>>>>>>>
> >>>>>>>> Note that whatever you allow might cause weaker isolation, in this
> >>>>>>>> case
> >>>>>>>> maybe real-time related.
> >>>>>>>>
> >>>>>>>> Henning
> >>>>>>>>
> >>>>>>>>> Adam
> >>>>>>>>>
> >>>>>>>
> >>>>>>> Hi,
> >>>>>>>
> >>>>>>> after allowing the access to 0x800-0x89f IO ports the issue with PIO
> >>>>>>> read is solved.
> >>>>>>>
> >>>>>>> Now I am facing issues with IOMMU/RAM, NMI IPI, MSR. Please see
> >>>>>>> attached log.
> >>>>>>
> >>>>>> You can again look at the system.map to find the code behind the MSR
> >>>>>> access.
> >>>>>>
> >>>>>> The rest can probably solved by consolidating some non-page aligned
> >>>>>> spreaded memory regions in your config -- could you please attach the
> >>>>>> output of jailhouse config collect? It should contain all data that is
> >>>>>> relevant for debugging.
> >>>>>>
> >>>>>> Thanks
> >>>>>> Ralf
> >>>>>>
> >>>>>>>
> >>>>>>> Any idea how to debug this?
> >>>>>>>
> >>>>>>> Adam
> >>>>>>>
> >>>>>
> >>>>> Hi,
> >>>>>
> >>>>> attached the jailhouse config collect output.
> >>>>
> >>>> Please try the attached config on next.
> >>>>
> >>>> You can use diff to see what I changed: I consolidated some memory
> >>>> regions to one large, contiguous region. Should at least solve the MMIO
> >>>> traps and the unknown instruction error.
> >>>>
> >>>> Remains the MSR access. What code is behind the instruction pointer?
> >>>>
> >>>> Thanks
> >>>> Ralf
> >>>>
> >>>>>
> >>>>> Adam
> >>>>>
> >>>
> >>> Hi,
> >>>
> >>> the attached config works fine regarding the IOMMU/RAM accesses. Thank
> >>> you!
> >>
> >> Great, good to hear.
> >>
> >>>
> >>> The function behind the RIP is native_read_msr_safe.
> >>
> >> Well... That doesn't help. :-)
> >>
> >> could you please
> >> $ echo #define CRASH_CELL_ON_PANIC 1 >> include/jailhouse/config.h
> >>
> >> and then recompile and reinstall jailhouse. This should give you a
> >> stacktrace of the kernel when the crash happens. Then we can go on
> >> debugging.
> >>
> >> Ralf
> >>
> >>>
> >>> Adam
> >>>
> >
> > Attached the dmesg with the kernel crash.
>
> Perfect. Try to add mce=off to your kernel command line.
>
> Ralf
>
> >
> > Adam
> >
Hi,
thank you for the hint. It solved the issue with MSR read.
After that there was some RAM/MMIO assignment and PIO access tuning required. I
am not sure about the PIO permission. Is it right to allow pic2 and APEI ERST?
+ [ 0xa0/8 ... 0xa7/8] = 0, /* pic2 */
+ [ 0xb0/8 ... 0xb7/8] = 0, /* APEI ERST */
There is still some issue with EFI access but it's not so critical.
Kind regards,
Adam
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>From b7975ec42c86f58c3e884c55f8447344837d6644 Mon Sep 17 00:00:00 2001
From: Adam Przybylski <[email protected]>
Date: Mon, 1 Jul 2019 07:23:30 +0200
Subject: [PATCH] Tuning for enabling root cell
* More RAM regions have to be assigned
* 2 additional PIO has to be allowed
* AMDIO/GPIO region has to be assigned
Signed-off-by: Adam Przybylski <[email protected]>
---
adam-amd.c | 40 +++++++++++++++++++++-------------------
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git a/adam-amd.c b/adam-amd.c
index a7be58d..29b8f54 100644
--- a/adam-amd.c
+++ b/adam-amd.c
@@ -123,29 +123,24 @@ struct {
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
- /* MemRegion: 76000000-d2afb017 : System RAM */
- /* MemRegion: d2afb018-d2b14457 : System RAM */
- /* MemRegion: d2b14458-d2b15017 : System RAM */
- /* MemRegion: d2b15018-d2b25857 : System RAM */
- /* MemRegion: d2b25858-d9036fff : System RAM */
- /* MemRegion: da49d000-da4b7fff : System RAM */
- /* MemRegion: da4b8000-da50ffff : ACPI Non-volatile Storage */
+ /* MemRegion: 76000000-d3f2e017 : System RAM */
+ /* MemRegion: d3f2e018-d3f47457 : System RAM */
+ /* MemRegion: d3f47458-d3f48017 : System RAM */
+ /* MemRegion: d3f48018-d3f59457 : System RAM */
+ /* MemRegion: d3f59458-d8c9afff : System RAM */
+ /* MemRegion: d8c9b000-da0fefff : APEI ERST */
+ /* MemRegion: da0ff000-da1c3fff : System RAM */
+ /* MemRegion: da1c4000-da52efff : ACPI Non-volatile Storage */
+ /* MemRegion: da52f000-dad7afff : User Space*/
+ /* MemRegion: dad7b000-dbffffff : System RAM */
{
.phys_start = 0x76000000,
.virt_start = 0x76000000,
- .size = 0x64510000,
+ .size = 0x66000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
- /* MemRegion: dad6b000-dbffffff : System RAM */
- {
- .phys_start = 0xdad6b000,
- .virt_start = 0xdad6b000,
- .size = 0x1295000,
- .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
- JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
- },
- /* MemRegion: ea900000-ea9fffff : ccp */
+ /* MemRegion: e2900000-e29fffff : ccp */
{
.phys_start = 0xe2900000,
.virt_start = 0xe2900000,
@@ -397,6 +392,13 @@ struct {
.size = 0x10000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
+ /* MemRegion: fed80000-fed8ffff : AMDI0030:00 */
+ {
+ .phys_start = 0xfed80000,
+ .virt_start = 0xfed80000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
/* MemRegion: 100000000-21f37ffff : System RAM */
{
.phys_start = 0x100000000,
@@ -538,8 +540,8 @@ struct {
[ 0x50/8 ... 0x57/8] = -1, /* timer1 */
[ 0x60/8 ... 0x67/8] = 0xec, /* NMI +NMI +keyboard */
[ 0x70/8 ... 0x77/8] = 0xfc, /* RTC */
- [ 0xa0/8 ... 0xa7/8] = -1, /* pic2 */
- [ 0xb0/8 ... 0xb7/8] = -1, /* APEI ERST */
+ [ 0xa0/8 ... 0xa7/8] = 0, /* pic2 */
+ [ 0xb0/8 ... 0xb7/8] = 0, /* APEI ERST */
[ 0x2f8/8 ... 0x2ff/8] = -1, /* serial */
[ 0x3b0/8 ... 0x3df/8] = 0, /* VGA */
[ 0x3f8/8 ... 0x3ff/8] = -1, /* serial */
--
2.21.0
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Copyright (c) Siemens AG, 2014-2017
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
* Alternatively, you can use or redistribute this file under the following
* BSD license:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* Configuration for GIGABYTE MZ01-CE1-00
* created with './tools/jailhouse config create -r /tmp/epyc/ adam-amd.c'
*
* NOTE: This config expects the following to be appended to your kernel cmdline
* "memmap=0x5200000$0x3a000000"
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_system header;
__u64 cpus[1];
struct jailhouse_memory mem_regions[53];
struct jailhouse_irqchip irqchips[5];
__u8 pio_bitmap[0x2000];
struct jailhouse_pci_device pci_devices[107];
struct jailhouse_pci_capability pci_caps[109];
} __attribute__((packed)) config = {
.header = {
.signature = JAILHOUSE_SYSTEM_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
.hypervisor_memory = {
.phys_start = 0x3a000000,
.size = 0x600000,
},
.debug_console = {
.address = 0x3f8,
.type = JAILHOUSE_CON_TYPE_8250,
.flags = JAILHOUSE_CON_ACCESS_PIO |
JAILHOUSE_CON_REGDIST_1,
},
.platform_info = {
.pci_mmconfig_base = 0xf0000000,
.pci_mmconfig_end_bus = 0x7f,
.x86 = {
.pm_timer_address = 0x808,
.vtd_interrupt_limit = 512,
.iommu_units = {
{
.base = 0xe7f00000,
.size = 0x80000,
.amd_bdf = 0x2,
.amd_base_cap = 0x40,
.amd_msi_cap = 0x64,
.amd_features = 0x80048f6f,
},
},
},
},
.root_cell = {
.name = "RootCell",
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.pio_bitmap_size = ARRAY_SIZE(config.pio_bitmap),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
.num_pci_caps = ARRAY_SIZE(config.pci_caps),
},
},
.cpus = {
0x000000000000ffff,
},
.mem_regions = {
/* MemRegion: 00000000-0009ffff : System RAM */
{
.phys_start = 0x0,
.virt_start = 0x0,
.size = 0xa0000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 00100000-39ffffff : System RAM */
{
.phys_start = 0x100000,
.virt_start = 0x100000,
.size = 0x39f00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 3f200000-75daffff : System RAM */
{
.phys_start = 0x3f200000,
.virt_start = 0x3f200000,
.size = 0x36bb0000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 76000000-d3f2e017 : System RAM */
/* MemRegion: d3f2e018-d3f47457 : System RAM */
/* MemRegion: d3f47458-d3f48017 : System RAM */
/* MemRegion: d3f48018-d3f59457 : System RAM */
/* MemRegion: d3f59458-d8c9afff : System RAM */
/* MemRegion: d8c9b000-da0fefff : APEI ERST */
/* MemRegion: da0ff000-da1c3fff : System RAM */
/* MemRegion: da1c4000-da52efff : ACPI Non-volatile Storage */
/* MemRegion: da52f000-dad7afff : User Space*/
/* MemRegion: dad7b000-dbffffff : System RAM */
{
.phys_start = 0x76000000,
.virt_start = 0x76000000,
.size = 0x66000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: e2900000-e29fffff : ccp */
{
.phys_start = 0xe2900000,
.virt_start = 0xe2900000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e2a01000-e2a01fff : ccp */
{
.phys_start = 0xe2a01000,
.virt_start = 0xe2a01000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e2b00000-e2bfffff : ccp */
{
.phys_start = 0xe2b00000,
.virt_start = 0xe2b00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e2c01000-e2c01fff : ccp */
{
.phys_start = 0xe2c01000,
.virt_start = 0xe2c01000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e2d00000-e2d7ffff : 0000:63:00.0 */
{
.phys_start = 0xe2d00000,
.virt_start = 0xe2d00000,
.size = 0x80000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e2d80000-e2d9ffff : 0000:63:00.0 */
{
.phys_start = 0xe2d80000,
.virt_start = 0xe2d80000,
.size = 0x20000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e2da0000-e2da3fff : ICH HD audio */
{
.phys_start = 0xe2da0000,
.virt_start = 0xe2da0000,
.size = 0x4000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e2e00000-e2e03fff : 0000:61:00.0 */
{
.phys_start = 0xe2e00000,
.virt_start = 0xe2e00000,
.size = 0x4000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e2f00000-e2f7ffff : igb */
{
.phys_start = 0xe2f00000,
.virt_start = 0xe2f00000,
.size = 0x80000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e2f81000-e2f83fff : igb */
{
.phys_start = 0xe2f81000,
.virt_start = 0xe2f81000,
.size = 0x3000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e3000000-e3002fff : nvme */
{
.phys_start = 0xe3000000,
.virt_start = 0xe3000000,
.size = 0x3000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e3100000-e317ffff : igb */
{
.phys_start = 0xe3100000,
.virt_start = 0xe3100000,
.size = 0x80000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e3181000-e3183fff : igb */
{
.phys_start = 0xe3181000,
.virt_start = 0xe3181000,
.size = 0x3000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: eb400000-eb4fffff : ccp */
{
.phys_start = 0xe7400000,
.virt_start = 0xe7400000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e7501000-e7501fff : ccp */
{
.phys_start = 0xe7501000,
.virt_start = 0xe7501000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e7600000-e76fffff : ccp */
{
.phys_start = 0xe7600000,
.virt_start = 0xe7600000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e7701000-e7701fff : ccp */
{
.phys_start = 0xe7701000,
.virt_start = 0xe7701000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e7a00000-e7afdfff : xhci-hcd */
{
.phys_start = 0xe7a00000,
.virt_start = 0xe7a00000,
.size = 0xfe000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e7aff000-e7afffff : xhci-hcd */
{
.phys_start = 0xe7aff000,
.virt_start = 0xe7aff000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e7b00000-e7bfffff : ccp */
{
.phys_start = 0xe7b00000,
.virt_start = 0xe7b00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e7c01000-e7c01fff : ccp */
{
.phys_start = 0xe7c01000,
.virt_start = 0xe7c01000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e7d00000-e7dfffff : ccp */
{
.phys_start = 0xe7d00000,
.virt_start = 0xe7d00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e7e01000-e7e01fff : ccp */
{
.phys_start = 0xe7e01000,
.virt_start = 0xe7e01000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: e7e02000-e7e02fff : ahci */
{
.phys_start = 0xe7e02000,
.virt_start = 0xe7e02000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: ec000000-edffffff : 0000:02:00.0 */
{
.phys_start = 0xec000000,
.virt_start = 0xec000000,
.size = 0x2000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: ee000000-ee01ffff : 0000:02:00.0 */
{
.phys_start = 0xee000000,
.virt_start = 0xee000000,
.size = 0x20000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: ee200000-ee2fdfff : xhci-hcd */
{
.phys_start = 0xee200000,
.virt_start = 0xee200000,
.size = 0xfe000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: ee2ff000-ee2fffff : xhci-hcd */
{
.phys_start = 0xee2ff000,
.virt_start = 0xee2ff000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: ee300000-ee3fffff : ccp */
{
.phys_start = 0xee300000,
.virt_start = 0xee300000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: ee401000-ee401fff : ccp */
{
.phys_start = 0xee401000,
.virt_start = 0xee401000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: ee500000-ee5fffff : ccp */
{
.phys_start = 0xee500000,
.virt_start = 0xee500000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: ee601000-ee601fff : ccp */
{
.phys_start = 0xee601000,
.virt_start = 0xee601000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: ee602000-ee602fff : ahci */
{
.phys_start = 0xee602000,
.virt_start = 0xee602000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fec01000-fec01fff : pnp 00:05 */
{
.phys_start = 0xfec01000,
.virt_start = 0xfec01000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fed00000-fed003ff : HPET 0 */
{
.phys_start = 0xfed00000,
.virt_start = 0xfed00000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fed61000-fed70fff : pnp 00:05 */
{
.phys_start = 0xfed61000,
.virt_start = 0xfed61000,
.size = 0x10000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fed80000-fed8ffff : AMDI0030:00 */
{
.phys_start = 0xfed80000,
.virt_start = 0xfed80000,
.size = 0x10000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 100000000-21f37ffff : System RAM */
{
.phys_start = 0x100000000,
.virt_start = 0x100000000,
.size = 0x11f380000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 220000000-41ff7ffff : System RAM */
{
.phys_start = 0x220000000,
.virt_start = 0x220000000,
.size = 0x1fff80000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 420000000-588ffffff : System RAM */
{
.phys_start = 0x420000000,
.virt_start = 0x420000000,
.size = 0x169000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 589000000-58cffffff : Kernel */
{
.phys_start = 0x589000000,
.virt_start = 0x589000000,
.size = 0x4000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 58d000000-61ff7ffff : System RAM */
{
.phys_start = 0x58d000000,
.virt_start = 0x58d000000,
.size = 0x92f80000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 620000000-81ff7ffff : System RAM */
{
.phys_start = 0x620000000,
.virt_start = 0x620000000,
.size = 0x1fff80000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: a00000000-a001fffff : 0000:63:00.0 */
{
.phys_start = 0xa00000000,
.virt_start = 0xa00000000,
.size = 0x200000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: c00000000-fffffffff : 0000:63:00.0 */
{
.phys_start = 0xc00000000,
.virt_start = 0xc00000000,
.size = 0x400000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 121d8000000-2168fffffff : PCI Bus 0000:40 */
{
.phys_start = 0x121d8000000,
.virt_start = 0x121d8000000,
.size = 0xf4b8000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 21690000000-30b47ffffff : PCI Bus 0000:20 */
{
.phys_start = 0x21690000000,
.virt_start = 0x21690000000,
.size = 0xf4b8000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 30b48000000-3ffffffffff : PCI Bus 0000:00 */
{
.phys_start = 0x30b48000000,
.virt_start = 0x30b48000000,
.size = 0xf4b8000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 3a600000-3f1fffff : JAILHOUSE Inmate Memory */
{
.phys_start = 0x3a600000,
.virt_start = 0x3a600000,
.size = 0x4c00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
},
.irqchips = {
/* IOAPIC 128, GSI base 0 */
{
.address = 0xfec00000,
.id = 0xa0,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
/* IOAPIC 129, GSI base 24 */
{
.address = 0xe7ff0000,
.id = 0x1,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
/* IOAPIC 130, GSI base 56 */
{
.address = 0xe79f0000,
.id = 0x0,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
/* IOAPIC 131, GSI base 88 */
{
.address = 0xe33f0000,
.id = 0x0,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
/* IOAPIC 132, GSI base 120 */
{
.address = 0xe28f0000,
.id = 0x0,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
},
.pio_bitmap = {
[ 0x0/8 ... 0x3f/8] = 0,
[ 0x40/8 ... 0x47/8] = 0xf0, /* PIT */
[ 0x50/8 ... 0x57/8] = -1, /* timer1 */
[ 0x60/8 ... 0x67/8] = 0xec, /* NMI +NMI +keyboard */
[ 0x70/8 ... 0x77/8] = 0xfc, /* RTC */
[ 0xa0/8 ... 0xa7/8] = 0, /* pic2 */
[ 0xb0/8 ... 0xb7/8] = 0, /* APEI ERST */
[ 0x2f8/8 ... 0x2ff/8] = -1, /* serial */
[ 0x3b0/8 ... 0x3df/8] = 0, /* VGA */
[ 0x3f8/8 ... 0x3ff/8] = -1, /* serial */
[ 0x408/8 ... 0x40f/8] = -1, /* pnp 00:05 */
[ 0x4d0/8 ... 0x4d7/8] = -1, /* pnp 00:05 +pnp 00:05 */
#if 0
[ 0x800/8 ... 0x807/8] = 0xc0, /* ACPI PM1a_EVT_BLK +ACPI PM1a_CNT_BLK */
[ 0x808/8 ... 0x80f/8] = 0xf0, /* ACPI PM_TMR */
[ 0x820/8 ... 0x827/8] = 0, /* ACPI GPE0_BLK */
#else
[ 0x800/8 ... 0x809/8] = 0,
#endif
[ 0xb00/8 ... 0xb0f/8] = -1, /* piix4_smbus */
[ 0xc00/8 ... 0xc07/8] = -1, /* pnp 00:05 */
[ 0xc10/8 ... 0xc17/8] = -1, /* pnp 00:05 */
[ 0xc50/8 ... 0xc57/8] = -1, /* pnp 00:05 +pnp 00:05 */
[ 0xc68/8 ... 0xc6f/8] = -1, /* pnp 00:05 +pnp 00:05 */
[ 0xca0/8 ... 0xca7/8] = -1, /* ipmi_si +ipmi_si */
[ 0xcd0/8 ... 0xcd7/8] = -1, /* pnp 00:05 +pnp 00:05 +pnp 00:05 +pnp 00:05 */
[ 0xcd8/8 ... 0xcdf/8] = -1, /* pnp 00:05 */
[ 0xcf8/8 ... 0xcff/8] = -1, /* PCI conf1 */
[ 0xd00/8 ... 0xffff/8] = 0, /* PCI bus */
},
.pci_devices = {
/* PCIDevice: 00:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.domain = 0x0,
.bdf = 0x0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:01.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x8,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:01.6 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xe,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 3,
.num_caps = 12,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:02.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x10,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:03.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x18,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:04.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x20,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:07.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x38,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:07.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x39,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:08.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x40,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:08.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x41,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:14.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xa0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:14.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xa3,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc1,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc2,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc3,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.4 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc4,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.5 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc5,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.6 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc6,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.7 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc7,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:19.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc8,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:19.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc9,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:19.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xca,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:19.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xcb,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:19.4 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xcc,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:19.5 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xcd,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:19.6 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xce,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:19.7 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xcf,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1a.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xd0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1a.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xd1,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1a.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xd2,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1a.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xd3,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1a.4 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xd4,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1a.5 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xd5,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1a.6 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xd6,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1a.7 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xd7,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1b.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xd8,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1b.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xd9,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1b.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xda,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1b.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xdb,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1b.4 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xdc,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1b.5 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xdd,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1b.6 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xde,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:1b.7 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xdf,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 01:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x100,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 24,
.num_caps = 6,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 02:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x200,
.bar_mask = {
0xfe000000, 0xfffe0000, 0xffffff80,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 30,
.num_caps = 2,
.num_msi_vectors = 2,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 03:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x300,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 32,
.num_caps = 7,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 03:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x302,
.bar_mask = {
0x00000000, 0x00000000, 0xfff00000,
0x00000000, 0x00000000, 0xffffe000,
},
.caps_start = 39,
.num_caps = 8,
.num_msi_vectors = 2,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 2,
.msix_region_size = 0x1000,
.msix_address = 0xee400000,
},
/* PCIDevice: 03:00.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x303,
.bar_mask = {
0xfff00000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 39,
.num_caps = 8,
.num_msi_vectors = 8,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 8,
.msix_region_size = 0x1000,
.msix_address = 0xee2fe000,
},
/* PCIDevice: 04:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x400,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 32,
.num_caps = 7,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 04:00.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x401,
.bar_mask = {
0x00000000, 0x00000000, 0xfff00000,
0x00000000, 0x00000000, 0xffffe000,
},
.caps_start = 39,
.num_caps = 8,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 1,
.msix_region_size = 0x1000,
.msix_address = 0xee600000,
},
/* PCIDevice: 04:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x402,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xfffff000,
},
.caps_start = 47,
.num_caps = 8,
.num_msi_vectors = 16,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 20:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2000,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 20:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2002,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 3,
.num_msi_vectors = 4,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 20:01.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2008,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 20:02.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2010,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 20:03.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2018,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 20:04.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2020,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 20:07.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2038,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 20:07.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2039,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 20:08.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2040,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 20:08.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2041,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 21:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2100,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 32,
.num_caps = 7,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 21:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2102,
.bar_mask = {
0x00000000, 0x00000000, 0xfff00000,
0x00000000, 0x00000000, 0xffffe000,
},
.caps_start = 39,
.num_caps = 8,
.num_msi_vectors = 2,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 2,
.msix_region_size = 0x1000,
.msix_address = 0xe7c00000,
},
/* PCIDevice: 21:00.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2103,
.bar_mask = {
0xfff00000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 39,
.num_caps = 8,
.num_msi_vectors = 8,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 8,
.msix_region_size = 0x1000,
.msix_address = 0xe7afe000,
},
/* PCIDevice: 22:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2200,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 32,
.num_caps = 7,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 22:00.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2201,
.bar_mask = {
0x00000000, 0x00000000, 0xfff00000,
0x00000000, 0x00000000, 0xffffe000,
},
.caps_start = 39,
.num_caps = 8,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 1,
.msix_region_size = 0x1000,
.msix_address = 0xe7e00000,
},
/* PCIDevice: 22:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x2202,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xfffff000,
},
.caps_start = 47,
.num_caps = 8,
.num_msi_vectors = 16,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 40:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4000,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 40:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4002,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 3,
.num_msi_vectors = 4,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 40:01.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4008,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 40:02.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4010,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 40:03.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4018,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 40:04.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4020,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 40:07.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4038,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 40:07.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4039,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 40:08.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4040,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 40:08.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4041,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 41:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4100,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 32,
.num_caps = 7,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 41:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4102,
.bar_mask = {
0x00000000, 0x00000000, 0xfff00000,
0x00000000, 0x00000000, 0xffffe000,
},
.caps_start = 39,
.num_caps = 8,
.num_msi_vectors = 2,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 2,
.msix_region_size = 0x1000,
.msix_address = 0xe7700000,
},
/* PCIDevice: 42:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4200,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 32,
.num_caps = 7,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 42:00.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x4201,
.bar_mask = {
0x00000000, 0x00000000, 0xfff00000,
0x00000000, 0x00000000, 0xffffe000,
},
.caps_start = 39,
.num_caps = 8,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 1,
.msix_region_size = 0x1000,
.msix_address = 0xe7500000,
},
/* PCIDevice: 60:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6000,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6002,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 3,
.num_msi_vectors = 4,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:01.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6008,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:01.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6009,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 3,
.num_caps = 12,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:02.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6010,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:03.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6018,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:03.2 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x601a,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 3,
.num_caps = 12,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:03.3 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x601b,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 3,
.num_caps = 12,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:03.4 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x601c,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 3,
.num_caps = 12,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:04.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6020,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:07.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6038,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:07.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6039,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:08.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6040,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 60:08.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6041,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 15,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 61:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6100,
.bar_mask = {
0xffffc000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 55,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 62:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6200,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 64,
.num_caps = 8,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 63:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6300,
.bar_mask = {
0x00000000, 0xfffffffc, 0xffe00000,
0xffffffff, 0xffffff00, 0xfff80000,
},
.caps_start = 72,
.num_caps = 13,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 63:00.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6301,
.bar_mask = {
0xffffc000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 85,
.num_caps = 7,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 64:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6400,
.bar_mask = {
0xfff80000, 0x00000000, 0xffffffe0,
0xffffc000, 0x00000000, 0x00000000,
},
.caps_start = 92,
.num_caps = 7,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 1,
.num_msix_vectors = 5,
.msix_region_size = 0x1000,
.msix_address = 0xe3180000,
},
/* PCIDevice: 65:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6500,
.bar_mask = {
0xffffc000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 99,
.num_caps = 10,
.num_msi_vectors = 32,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 33,
.msix_region_size = 0x1000,
.msix_address = 0xe3003000,
},
/* PCIDevice: 66:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6600,
.bar_mask = {
0xfff80000, 0x00000000, 0xffffffe0,
0xffffc000, 0x00000000, 0x00000000,
},
.caps_start = 92,
.num_caps = 7,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 1,
.num_msix_vectors = 5,
.msix_region_size = 0x1000,
.msix_address = 0xe2f80000,
},
/* PCIDevice: 67:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6700,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 32,
.num_caps = 7,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 67:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6702,
.bar_mask = {
0x00000000, 0x00000000, 0xfff00000,
0x00000000, 0x00000000, 0xffffe000,
},
.caps_start = 39,
.num_caps = 8,
.num_msi_vectors = 2,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 2,
.msix_region_size = 0x1000,
.msix_address = 0xe2c00000,
},
/* PCIDevice: 68:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6800,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 32,
.num_caps = 7,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 68:00.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x6801,
.bar_mask = {
0x00000000, 0x00000000, 0xfff00000,
0x00000000, 0x00000000, 0xffffe000,
},
.caps_start = 39,
.num_caps = 8,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 1,
.msix_region_size = 0x1000,
.msix_address = 0xe2a00000,
},
},
.pci_caps = {
/* PCIDevice: 00:00.2 */
/* PCIDevice: 20:00.2 */
/* PCIDevice: 40:00.2 */
/* PCIDevice: 60:00.2 */
{
.id = PCI_CAP_ID_SECDEV,
.start = 0x40,
.len = 2,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0x64,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_HT,
.start = 0x74,
.len = 2,
.flags = 0,
},
/* PCIDevice: 00:01.6 */
/* PCIDevice: 60:01.1 */
/* PCIDevice: 60:03.2 */
/* PCIDevice: 60:03.3 */
/* PCIDevice: 60:03.4 */
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 60,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_SSVID,
.start = 0xc0,
.len = 2,
.flags = 0,
},
{
.id = PCI_CAP_ID_HT,
.start = 0xc8,
.len = 2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x370,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_DPC | JAILHOUSE_PCI_EXT_CAP,
.start = 0x380,
.len = 4,
.flags = 0,
},
{
.id = 0x23 | JAILHOUSE_PCI_EXT_CAP,
.start = 0x3c4,
.len = 4,
.flags = 0,
},
/* PCIDevice: 00:07.1 */
/* PCIDevice: 00:08.1 */
/* PCIDevice: 20:07.1 */
/* PCIDevice: 20:08.1 */
/* PCIDevice: 40:07.1 */
/* PCIDevice: 40:08.1 */
/* PCIDevice: 60:07.1 */
/* PCIDevice: 60:08.1 */
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 60,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_SSVID,
.start = 0xc0,
.len = 2,
.flags = 0,
},
{
.id = PCI_CAP_ID_HT,
.start = 0xc8,
.len = 2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 4,
.flags = 0,
},
/* PCIDevice: 01:00.0 */
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x78,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x80,
.len = 60,
.flags = 0,
},
{
.id = PCI_CAP_ID_SSVID,
.start = 0xc0,
.len = 2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VC | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x800,
.len = 4,
.flags = 0,
},
/* PCIDevice: 02:00.0 */
{
.id = PCI_CAP_ID_PM,
.start = 0x40,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
/* PCIDevice: 03:00.0 */
/* PCIDevice: 04:00.0 */
/* PCIDevice: 21:00.0 */
/* PCIDevice: 22:00.0 */
/* PCIDevice: 41:00.0 */
/* PCIDevice: 42:00.0 */
/* PCIDevice: 67:00.0 */
/* PCIDevice: 68:00.0 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 60,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 4,
.flags = 0,
},
/* PCIDevice: 03:00.2 */
/* PCIDevice: 03:00.3 */
/* PCIDevice: 04:00.1 */
/* PCIDevice: 21:00.2 */
/* PCIDevice: 21:00.3 */
/* PCIDevice: 22:00.1 */
/* PCIDevice: 41:00.2 */
/* PCIDevice: 42:00.1 */
/* PCIDevice: 67:00.2 */
/* PCIDevice: 68:00.1 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 60,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSIX,
.start = 0xc0,
.len = 12,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 4,
.flags = 0,
},
/* PCIDevice: 04:00.2 */
/* PCIDevice: 22:00.2 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 60,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_SATA,
.start = 0xd0,
.len = 2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 4,
.flags = 0,
},
/* PCIDevice: 61:00.0 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 60,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_LTR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x320,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x370,
.len = 4,
.flags = 0,
},
/* PCIDevice: 62:00.0 */
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 60,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_SSVID,
.start = 0xc0,
.len = 2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 4,
.flags = 0,
},
/* PCIDevice: 63:00.0 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 60,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_REBAR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x200,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ATS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2b0,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_PRI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2c0,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_PASID | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2d0,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_LTR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x320,
.len = 4,
.flags = 0,
},
/* PCIDevice: 63:00.1 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 60,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 4,
.flags = 0,
},
/* PCIDevice: 64:00.0 */
/* PCIDevice: 66:00.0 */
{
.id = PCI_CAP_ID_PM,
.start = 0x40,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 24,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSIX,
.start = 0x70,
.len = 12,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0xa0,
.len = 60,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_DSN | JAILHOUSE_PCI_EXT_CAP,
.start = 0x140,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_TPH | JAILHOUSE_PCI_EXT_CAP,
.start = 0x1a0,
.len = 4,
.flags = 0,
},
/* PCIDevice: 65:00.0 */
{
.id = PCI_CAP_ID_PM,
.start = 0x40,
.len = 8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 14,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x70,
.len = 60,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSIX,
.start = 0xb0,
.len = 12,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_DSN | JAILHOUSE_PCI_EXT_CAP,
.start = 0x148,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_PWR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x158,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x168,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_LTR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x188,
.len = 4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x190,
.len = 4,
.flags = 0,
},
},
};
