From: Jan Kiszka <[email protected]> Lots of things changed since the file was last touched. Add the hypercall ABIs for non-Intel-x86, update the "CPU Get Info" hypercall with new statistic types, and extend the Comm Region description with the console and non-x86 extensions added meanwhile.
Signed-off-by: Jan Kiszka <[email protected]> --- Documentation/hypervisor-interfaces.txt | 152 ++++++++++++++++++++++++++------ 1 file changed, 125 insertions(+), 27 deletions(-) diff --git a/Documentation/hypervisor-interfaces.txt b/Documentation/hypervisor-interfaces.txt index f29bac43..74982e9d 100644 --- a/Documentation/hypervisor-interfaces.txt +++ b/Documentation/hypervisor-interfaces.txt @@ -13,7 +13,8 @@ Detection --------- This interface is useful for cell code that should work not only inside a -Jailhouse cell. The ABI is architecture specific. +Jailhouse cell. The ABI is architecture specific. So far, it is only available +for x86. x86 ABI @@ -63,16 +64,36 @@ a similar channel. Details of the hypercall ABI are architecture specific and will be defined in the following. -Intel x86 (IA-32/32e) ABI -- - - - - - - - - - - - - +x86 ABI +- - - - -Instruction: vmcall +Instruction: vmcall (IA-32/32e) / vmmcall (AMD64) Hypercall code: EAX -1. argument: RDI (IA-32e) / EDI (IA-32) -2. argument: RSI (IA-32e) / ESI (IA-32) +1. argument: RDI (64-bit mode) / EDI (32-bit mode) +2. argument: RSI (64-bit mode) / ESI (32-bit mode) Return code: EAX +ARMv7 ABI +- - - - - + +Instruction: hvc #0x4a48 +Hypercall code: r0 +1. argument: r1 +2. argument: r2 +Return code: r0 + + +ARMv8 ABI +- - - - - + +Instruction: hvc #0x4a48 +Hypercall code: x0 +1. argument: x1 +2. argument: x2 +Return code: x0 + + Hypercall "Disable" (code 0) - - - - - - - - - - - - - - - @@ -230,14 +251,31 @@ Hypercall "CPU Get Info" (code 7) Obtain information about a specific CPU. Arguments: 1. Logical ID of CPU to be queried - 2. Information type: + 2. Generic information type: 0 - CPU state 1000 - Total number of VM exits - 1001 - VM exits due to MMIO access - 1002 - VM exits due to PIO access - 1003 - VM exits due to IPI submissions - 1004 - VM exits due to management events - 1005 - VM exits due to hypercalls + 1001 - VM exits due to MMIO accesses + 1002 - VM exits due to management events + 1003 - VM exits due to hypercalls + + x86-specific type: + + 1004 - VM exits due to PIO accesses + 1005 - VM exits due to xAPIC accesses + 1006 - VM exits due to CR accesses + 1007 - VM exits due to CPUID instructions + 1008 - VM exits due to XSETBV instructions + 1009 - VM exits due to exceptions + 1010 - VM exits due to unspecified MSR accesses + 1011 - VM exits due to x2APIC ICR MSR accesses + + ARMv7/ARMv8-specific type: + + 1004 - VM exits due to IRQ injections + 1005 - VM exits due to SGI injections + 1006 - VM exits due to PSCI calls + 1007 - VM exits due to SMCCC calls + 1008 - VM exits due to CP15 accesses (only ARMv7) Statistic counters are reset when a CPU is assigned to a different cell. The total number of VM exits may be different from the sum of all specific VM exit @@ -295,8 +333,9 @@ Communication region layout +------------------------------+ | Message from Cell (32 bit) | +------------------------------+ - | Reserved (32 bit) | + : Generic Platform Information : +------------------------------+ + : Architecture-specific : : Platform Information : +------------------------------+ - higher address @@ -305,7 +344,7 @@ Platform Information part is architecture-specific. Its content is filled by the hypervisor during cell creation and shall be considered read-only until cell destruction. -The ABI revision described here is 0. Future versions may not use a compatible +The ABI revision described here is 2. Future versions may not use a compatible layout or field semantic, except for the fields "Signature", "ABI Revision" and "Cell State". @@ -385,22 +424,80 @@ to destroy or restart that cell. On restart, it will also reset the state field to "Running". +Generic Platform Information +- - - - - - - - - - - - - - - + + +--------------------------------------+ - begin of communication region + : header, see above : (lower address) + +--------------------------------------+ + | Information Flags (32 bit) | + +--------------------------------------+ + | Console Address (64 bit) | + +--------------------------------------+ + | Console Size (32 bit) | + +--------------------------------------+ + | Console Type (16 bit) | + +--------------------------------------+ + | Console Flags (16 bit) | + +--------------------------------------+ + | Console UART Divider (32 bit) | + +--------------------------------------+ + | Console UART Gate No. (32 bit) | + +--------------------------------------+ + | Console UART Clock Register (64 bit) | + +--------------------------------------+ + | PCI MMCONFIG Address (64 bit) | + +--------------------------------------+ + : Architecture-specific : + : Platform Information : + +--------------------------------------+ - higher address + +The Information Flags field defines two bits so far: Bit 0 is set when the cell +may use the Debug Console putc hypercall. Bit 1 is set when the cell shall use +the Debug Console putc hypercall as output console. Other bits in this field +are reserved. + +See [3] for a description of the console fields. + + Platform Information for x86 - - - - - - - - - - - - - - - - +----------------------------------+ - begin of communication region - : generic part, see above : (lower address) - +----------------------------------+ - | PCI MMCONFIG Address (64 bit) | - +----------------------------------+ - | PM Timer Address (16 bit) | - +----------------------------------+ - | Number of CPUs (16 bit) | - +----------------------------------+ - | TSC Frequency in kHz (32 bit) | - +----------------------------------+ - | APIC Timer Freq. in kHz (32 bit) | - +----------------------------------+ - higher address + +--------------------------------------+ - begin of communication region + : header, see above : (lower address) + +--------------------------------------+ + : generic information, see above : + +--------------------------------------+ + | PM Timer Address (16 bit) | + +--------------------------------------+ + | Number of CPUs (16 bit) | + +--------------------------------------+ + | TSC Frequency in kHz (32 bit) | + +--------------------------------------+ + | APIC Timer Frequency in kHz (32 bit) | + +--------------------------------------+ - higher address + + +Platform Information for ARMv7 and ARMv8 +- - - - - - - - - - - - - - - - - - - - - + + +--------------------------------------+ - begin of communication region + : header, see above : (lower address) + +--------------------------------------+ + : generic information, see above : + +--------------------------------------+ + | GIC Version (8 bit) | + +--------------------------------------+ + | Reserved (56 bit) | + +--------------------------------------+ + | GIC Distributor Address (64 bit) | + +--------------------------------------+ + | GIC CPU Interface Address (64 bit) | + +--------------------------------------+ + | GIC Redistributor Address (64 bit) | + +--------------------------------------+ + | Virtual PCI Host IRQ Base (32 bit) | + +--------------------------------------+ - higher address References @@ -408,3 +505,4 @@ References [1] Documentation/cell-environments.txt [2] Documentation/configuration-format.txt +[3] Documentation/debug-output.md -- 2.16.4 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. 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