Branch: refs/heads/wip/riscv
Home: https://github.com/siemens/jailhouse
Commit: 536441a05729b94446ff2a1f1ce0383306ffe822
https://github.com/siemens/jailhouse/commit/536441a05729b94446ff2a1f1ce0383306ffe822
Author: Jan Kiszka <[email protected]>
Date: 2020-02-15 (Sat, 15 Feb 2020)
Changed paths:
A configs/riscv/qemu-riscv64.c
A hypervisor/arch/riscv/Kbuild
A hypervisor/arch/riscv/Makefile
A hypervisor/arch/riscv/asm-defines.c
A hypervisor/arch/riscv/control.c
A hypervisor/arch/riscv/dbg-write.c
A hypervisor/arch/riscv/entry.S
A hypervisor/arch/riscv/include/asm/bitops.h
A hypervisor/arch/riscv/include/asm/cell.h
A hypervisor/arch/riscv/include/asm/control.h
A hypervisor/arch/riscv/include/asm/ivshmem.h
A hypervisor/arch/riscv/include/asm/jailhouse_header.h
A hypervisor/arch/riscv/include/asm/mmio.h
A hypervisor/arch/riscv/include/asm/paging.h
A hypervisor/arch/riscv/include/asm/paging_modes.h
A hypervisor/arch/riscv/include/asm/percpu.h
A hypervisor/arch/riscv/include/asm/processor.h
A hypervisor/arch/riscv/include/asm/sections.h
A hypervisor/arch/riscv/include/asm/spinlock.h
A hypervisor/arch/riscv/include/asm/types.h
A hypervisor/arch/riscv/ivshmem.c
A hypervisor/arch/riscv/lib.c
A hypervisor/arch/riscv/paging.c
A hypervisor/arch/riscv/pci.c
A hypervisor/arch/riscv/setup.c
A include/arch/riscv/asm/jailhouse_hypercall.h
A inmates/demos/riscv/Makefile
A inmates/lib/riscv/Makefile
A inmates/tests/riscv/Makefile
A inmates/tools/riscv/Makefile
M scripts/include.mk
Log Message:
-----------
RISC-V cornerstone
This allows to build Jailhouse for RISC-V, using QEMU as a first target.
The assembly entry routine can be called and returns a funky error for
now. All the rest are stubs.
Signed-off-by: Jan Kiszka <[email protected]>
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