Re: [PATCH 0/2] boot jailhouse before root cell linux

Thu, 05 Mar 2020 03:06:26 -0800 


On 05/03/20 3:09 PM, [email protected] wrote:
> From: Peng Fan <[email protected]>
> 
> This patchset tested on i.MX8MN arm64 with quad A53 cores
> 
> Patch 1 is to align jailhouse_system. Since the loader not have
> MMU enabled, unaligned access will cause abort.
> 
> Patch 2 is not that well orgnized. It does GICv3 initialization,
> SMP boot up. Then kick inmate cell and root cell.
> Some code are hardcoding for now.
> 
> The boot log as below, you could see root linux and gic demo both running:
> root cell not able to manage inmate cell for now. But I think it
> could be supported. intercell communication not aded currently.
> 
> From test log, linux root cell boot will cause large latency for gic-demo
> jitter.
> 
> It maybe good to use cache color on ARMv8, but still have issues
> for root cell DMA without SMMU.
> 

[..snip..]

Nice to see this being supported...!!!

> Timer fired, jitter:    749 ns, min:    749 ns, max:   7999 ns
> [    0.127643] Detected VIPT I-cache on CPU1
> [    0.127671] GICv3: CPU1: found redistributor 1 region 0:0x00000000388a0000
> [    0.127700] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
> [    0.159684] Detected VIPT I-cache on CPU2
> [    0.159700] GICv3: CPU2: found redistributor 2 region 0:0x00000000388c0000
> [    0.159717] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
> [    0.191721] psci: failed to boot CPU3 (-1)
> [    0.227974] CPU3: failed to boot: -1
> [    0.231609] smp: Brought up 1 node, 3 CPUs

Did not look closer but couple of questions:
- I guess the above CPU is given to inmate cell. We should be able to handle
this error gracefully rather than failure. Wondering how other hypervisors
handle this.
- What level of features supported when compared with type 2?

Thanks and regards,
Lokesh

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