On Tue, Mar 31, 2020 at 6:44 PM Andrew Cooper <andrew.coop...@citrix.com> wrote:
>
> On 31/03/2020 23:23, Brian Gerst wrote:
> > On Tue, Mar 31, 2020 at 1:59 PM Andrew Cooper <andrew.coop...@citrix.com>
> > wrote:
> >> Linux has an implementation of the Universal Start-up Algorithm (MP spec,
> >> Appendix B.4, Application Processor Startup), which includes
> >> unconditionally
> >> writing to the Bios Data Area and CMOS registers.
> >>
> >> The warm reset vector is only necessary in the non-integrated Local APIC
> >> case.
> >> UV and Jailhouse already have an opt-out for this behaviour, but blindly
> >> using
> >> the BDA and CMOS on a UEFI or other reduced hardware system isn't clever.
> >>
> >> We could make this conditional on the integrated-ness of the Local APIC,
> >> but
> >> 486-era SMP isn't supported. Drop the logic completely, tidying up the
> >> includ
> >> list and header files as appropriate.
> >>
> >> CC: Thomas Gleixner <t...@linutronix.de>
> >> CC: Ingo Molnar <mi...@redhat.com>
> >> CC: Borislav Petkov <b...@alien8.de>
> >> CC: "H. Peter Anvin" <h...@zytor.com>
> >> CC: x...@kernel.org
> >> CC: Jan Kiszka <jan.kis...@siemens.com>
> >> CC: James Morris <jmor...@namei.org>
> >> CC: David Howells <dhowe...@redhat.com>
> >> CC: Andrew Cooper <andrew.coop...@citrix.com>
> >> CC: Matthew Garrett <mj...@google.com>
> >> CC: Josh Boyer <jwbo...@redhat.com>
> >> CC: Steve Wahl <steve.w...@hpe.com>
> >> CC: Mike Travis <mike.tra...@hpe.com>
> >> CC: Dimitri Sivanich <dimitri.sivan...@hpe.com>
> >> CC: Arnd Bergmann <a...@arndb.de>
> >> CC: "Peter Zijlstra (Intel)" <pet...@infradead.org>
> >> CC: Giovanni Gherdovich <ggherdov...@suse.cz>
> >> CC: "Rafael J. Wysocki" <rafael.j.wyso...@intel.com>
> >> CC: Len Brown <len.br...@intel.com>
> >> CC: Kees Cook <keesc...@chromium.org>
> >> CC: Martin Molnar <martin.molnar.programm...@gmail.com>
> >> CC: Pingfan Liu <kernelf...@gmail.com>
> >> CC: linux-ker...@vger.kernel.org
> >> CC: jailhouse-dev@googlegroups.com
> >> Suggested-by: "H. Peter Anvin" <h...@zytor.com>
> >> Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
> >> ---
> >> v2:
> >> * Drop logic entirely, rather than retaining support in 32bit builds.
> >> ---
> >> arch/x86/include/asm/apic.h | 6 -----
> >> arch/x86/include/asm/x86_init.h | 1 -
> >> arch/x86/kernel/apic/x2apic_uv_x.c | 1 -
> >> arch/x86/kernel/jailhouse.c | 1 -
> >> arch/x86/kernel/platform-quirks.c | 1 -
> >> arch/x86/kernel/smpboot.c | 50
> >> --------------------------------------
> >> 6 files changed, 60 deletions(-)
> >>
> >> diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
> >> index 19e94af9cc5d..5c33f9374b28 100644
> >> --- a/arch/x86/include/asm/apic.h
> >> +++ b/arch/x86/include/asm/apic.h
> >> @@ -472,12 +472,6 @@ static inline unsigned default_get_apic_id(unsigned
> >> long x)
> >> return (x >> 24) & 0x0F;
> >> }
> >>
> >> -/*
> >> - * Warm reset vector position:
> >> - */
> >> -#define TRAMPOLINE_PHYS_LOW 0x467
> >> -#define TRAMPOLINE_PHYS_HIGH 0x469
> >> -
> >> extern void generic_bigsmp_probe(void);
> >>
> >> #ifdef CONFIG_X86_LOCAL_APIC
> >> diff --git a/arch/x86/include/asm/x86_init.h
> >> b/arch/x86/include/asm/x86_init.h
> >> index 96d9cd208610..006a5d7fd7eb 100644
> >> --- a/arch/x86/include/asm/x86_init.h
> >> +++ b/arch/x86/include/asm/x86_init.h
> >> @@ -229,7 +229,6 @@ enum x86_legacy_i8042_state {
> >> struct x86_legacy_features {
> >> enum x86_legacy_i8042_state i8042;
> >> int rtc;
> >> - int warm_reset;
> >> int no_vga;
> >> int reserve_bios_regions;
> >> struct x86_legacy_devices devices;
> >> diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c
> >> b/arch/x86/kernel/apic/x2apic_uv_x.c
> >> index ad53b2abc859..5afcfd193592 100644
> >> --- a/arch/x86/kernel/apic/x2apic_uv_x.c
> >> +++ b/arch/x86/kernel/apic/x2apic_uv_x.c
> >> @@ -343,7 +343,6 @@ static int __init uv_acpi_madt_oem_check(char
> >> *_oem_id, char *_oem_table_id)
> >> } else if (!strcmp(oem_table_id, "UVH")) {
> >> /* Only UV1 systems: */
> >> uv_system_type = UV_NON_UNIQUE_APIC;
> >> - x86_platform.legacy.warm_reset = 0;
> >> __this_cpu_write(x2apic_extra_bits, pnodeid <<
> >> uvh_apicid.s.pnode_shift);
> >> uv_set_apicid_hibit();
> >> uv_apic = 1;
> >> diff --git a/arch/x86/kernel/jailhouse.c b/arch/x86/kernel/jailhouse.c
> >> index 6eb8b50ea07e..d628fe92d6af 100644
> >> --- a/arch/x86/kernel/jailhouse.c
> >> +++ b/arch/x86/kernel/jailhouse.c
> >> @@ -210,7 +210,6 @@ static void __init jailhouse_init_platform(void)
> >> x86_platform.calibrate_tsc = jailhouse_get_tsc;
> >> x86_platform.get_wallclock = jailhouse_get_wallclock;
> >> x86_platform.legacy.rtc = 0;
> >> - x86_platform.legacy.warm_reset = 0;
> >> x86_platform.legacy.i8042 = X86_LEGACY_I8042_PLATFORM_ABSENT;
> >>
> >> legacy_pic = &null_legacy_pic;
> >> diff --git a/arch/x86/kernel/platform-quirks.c
> >> b/arch/x86/kernel/platform-quirks.c
> >> index b348a672f71d..d922c5e0c678 100644
> >> --- a/arch/x86/kernel/platform-quirks.c
> >> +++ b/arch/x86/kernel/platform-quirks.c
> >> @@ -9,7 +9,6 @@ void __init x86_early_init_platform_quirks(void)
> >> {
> >> x86_platform.legacy.i8042 = X86_LEGACY_I8042_EXPECTED_PRESENT;
> >> x86_platform.legacy.rtc = 1;
> >> - x86_platform.legacy.warm_reset = 1;
> >> x86_platform.legacy.reserve_bios_regions = 0;
> >> x86_platform.legacy.devices.pnpbios = 1;
> >>
> >> diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
> >> index fe3ab9632f3b..a9f5b511d0b4 100644
> >> --- a/arch/x86/kernel/smpboot.c
> >> +++ b/arch/x86/kernel/smpboot.c
> >> @@ -72,7 +72,6 @@
> >> #include <asm/fpu/internal.h>
> >> #include <asm/setup.h>
> >> #include <asm/uv/uv.h>
> >> -#include <linux/mc146818rtc.h>
> >> #include <asm/i8259.h>
> >> #include <asm/misc.h>
> >> #include <asm/qspinlock.h>
> >> @@ -119,34 +118,6 @@ int arch_update_cpu_topology(void)
> >> return retval;
> >> }
> >>
> >> -static inline void smpboot_setup_warm_reset_vector(unsigned long
> >> start_eip)
> >> -{
> >> - unsigned long flags;
> >> -
> >> - spin_lock_irqsave(&rtc_lock, flags);
> >> - CMOS_WRITE(0xa, 0xf);
> >> - spin_unlock_irqrestore(&rtc_lock, flags);
> >> - *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
> >> - start_eip >> 4;
> >> - *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
> >> - start_eip & 0xf;
> >> -}
> >> -
> >> -static inline void smpboot_restore_warm_reset_vector(void)
> >> -{
> >> - unsigned long flags;
> >> -
> >> - /*
> >> - * Paranoid: Set warm reset code and vector here back
> >> - * to default values.
> >> - */
> >> - spin_lock_irqsave(&rtc_lock, flags);
> >> - CMOS_WRITE(0, 0xf);
> >> - spin_unlock_irqrestore(&rtc_lock, flags);
> >> -
> >> - *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
> >> -}
> >> -
> >> static void init_freq_invariance(void);
> >>
> >> /*
> >> @@ -1049,20 +1020,6 @@ static int do_boot_cpu(int apicid, int cpu, struct
> >> task_struct *idle,
> >> * the targeted processor.
> >> */
> >>
> >> - if (x86_platform.legacy.warm_reset) {
> >> -
> >> - pr_debug("Setting warm reset code and vector.\n");
> >> -
> >> - smpboot_setup_warm_reset_vector(start_ip);
> >> - /*
> >> - * Be paranoid about clearing APIC errors.
> >> - */
> >> - if (APIC_INTEGRATED(boot_cpu_apic_version)) {
> >> - apic_write(APIC_ESR, 0);
> >> - apic_read(APIC_ESR);
> >> - }
> >> - }
> >> -
> >> /*
> >> * AP might wait on cpu_callout_mask in cpu_init() with
> >> * cpu_initialized_mask set if previous attempt to online
> >> @@ -1118,13 +1075,6 @@ static int do_boot_cpu(int apicid, int cpu, struct
> >> task_struct *idle,
> >> }
> >> }
> >>
> >> - if (x86_platform.legacy.warm_reset) {
> >> - /*
> >> - * Cleanup possible dangling ends...
> >> - */
> >> - smpboot_restore_warm_reset_vector();
> >> - }
> >> -
> >> return boot_error;
> >> }
> > You removed x86_platform.legacy.warm_reset in the original patch, but
> > that is missing in V2.
>
> Second hunk? Or are you referring to something different?
Removing the warm_reset field from struct x86_legacy_features.
--
Brian Gerst
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