Signed-off-by: Alice Guo <[email protected]> --- configs/arm64/imx8mq-inmate-demo.c | 70 +++++++++++-- configs/arm64/imx8mq-linux-demo.c | 158 +++++++++++++++++++++++++++++ configs/arm64/imx8mq.c | 93 +++++++++++++++-- 3 files changed, 307 insertions(+), 14 deletions(-) create mode 100644 configs/arm64/imx8mq-linux-demo.c
diff --git a/configs/arm64/imx8mq-inmate-demo.c b/configs/arm64/imx8mq-inmate-demo.c index 8c1ad624..39b74593 100644 --- a/configs/arm64/imx8mq-inmate-demo.c +++ b/configs/arm64/imx8mq-inmate-demo.c @@ -1,7 +1,7 @@ /* * iMX8MQ target - inmate demo * - * Copyright NXP 2018 + * Copyright 2020 NXP * * Authors: * Peng Fan <[email protected]> @@ -16,7 +16,9 @@ struct { struct jailhouse_cell_desc cell; __u64 cpus[1]; - struct jailhouse_memory mem_regions[3]; + struct jailhouse_memory mem_regions[8]; + struct jailhouse_irqchip irqchips[1]; + struct jailhouse_pci_device pci_devices[1]; } __attribute__((packed)) config = { .cell = { .signature = JAILHOUSE_CELL_DESC_SIGNATURE, @@ -26,8 +28,9 @@ struct { .cpu_set_size = sizeof(config.cpus), .num_memory_regions = ARRAY_SIZE(config.mem_regions), - .num_irqchips = 0, - .num_pci_devices = 0, + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .vpci_irq_base = 108, .console = { .address = 0x30860000, @@ -42,6 +45,38 @@ struct { }, .mem_regions = { + /* IVHSMEM shared memory region for 00:00.0 */ { + .phys_start = 0xbfd00000, + .virt_start = 0xbfd00000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xbfd01000, + .virt_start = 0xbfd01000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xbfd0a000, + .virt_start = 0xbfd0a000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xbfd0c000, + .virt_start = 0xbfd0c000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xbfd0e000, + .virt_start = 0xbfd0e000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, /* UART1 */ { .phys_start = 0x30860000, .virt_start = 0x30860000, @@ -50,7 +85,7 @@ struct { JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, }, /* RAM: Top at 4GB Space */ { - .phys_start = 0xffaf0000, + .phys_start = 0xc0000000, .virt_start = 0, .size = 0x00010000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | @@ -62,5 +97,28 @@ struct { .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_COMM_REGION, }, - } + }, + + .irqchips = { + /* GIC */ { + .address = 0x38800000, + .pin_base = 128, + .pin_bitmap = { + 0x1 << (108 + 32 - 128) /* SPI 109 */ + }, + }, + }, + + .pci_devices = { + { /* IVSHMEM 00:00.0 (demo) */ + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 1, + .shmem_peers = 1, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + }, }; diff --git a/configs/arm64/imx8mq-linux-demo.c b/configs/arm64/imx8mq-linux-demo.c new file mode 100644 index 00000000..a59dd934 --- /dev/null +++ b/configs/arm64/imx8mq-linux-demo.c @@ -0,0 +1,158 @@ +/* + * iMX8MQ target - linux-demo + * + * Copyright 2018 NXP + * + * Authors: + * Peng Fan <[email protected]> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[15]; + struct jailhouse_irqchip irqchips[2]; + struct jailhouse_pci_device pci_devices[2]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "linux-inmate-demo", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .vpci_irq_base = 108, /* Not include 32 base */ + }, + + .cpus = { + 0xc, + }, + + .mem_regions = { + /* IVHSMEM shared memory region for 00:00.0 */ { + .phys_start = 0xbfd00000, + .virt_start = 0xbfd00000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xbfd01000, + .virt_start = 0xbfd01000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xbfd0a000, + .virt_start = 0xbfd0a000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xbfd0c000, + .virt_start = 0xbfd0c000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0xbfd0e000, + .virt_start = 0xbfd0e000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + /* IVSHMEM shared memory regions for 00:01.0 (networking) */ + JAILHOUSE_SHMEM_NET_REGIONS(0xbfe00000, 1), + /* UART1 earlycon */ { + .phys_start = 0x30860000, + .virt_start = 0x30860000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* UART2 */ { + .phys_start = 0x30890000, + .virt_start = 0x30890000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* SHDC1 */ { + .phys_start = 0x30b40000, + .virt_start = 0x30b40000, + .size = 0x10000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* RAM: Top at 4GB Space */ { + .phys_start = 0xbff00000, + .virt_start = 0, + .size = 0x10000, /* 64KB */ + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + /* RAM: Top at 4GB Space */ { + .phys_start = 0xc0000000, + .virt_start = 0xc0000000, + .size = 0x3dc00000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA | + JAILHOUSE_MEM_LOADABLE, + }, + /* communication region */ { + .virt_start = 0x80000000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, + }, + + .irqchips = { + /* uart2/sdhc1 */ { + .address = 0x38800000, + .pin_base = 32, + .pin_bitmap = { + (1 << (27 + 32 - 32)) | (1 << (22 + 32 - 32)) + }, + }, + /* IVSHMEM */ { + .address = 0x38800000, + .pin_base = 128, + .pin_bitmap = { + 0x1 << (108 + 32 - 128) /* SPI 109 */ + }, + }, + }, + + .pci_devices = { + { /* IVSHMEM 00:00.0 (demo) */ + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 2, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + { /* IVSHMEM 00:01.0 (networking) */ + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 0, + .bdf = 1 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 5, + .shmem_dev_id = 1, + .shmem_peers = 2, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH, + }, + }, +}; diff --git a/configs/arm64/imx8mq.c b/configs/arm64/imx8mq.c index 7d113264..3292bd29 100644 --- a/configs/arm64/imx8mq.c +++ b/configs/arm64/imx8mq.c @@ -1,7 +1,7 @@ /* * i.MX8MQ Target * - * Copyright 2017 NXP + * Copyright 2017-2018 NXP * * Authors: * Peng Fan <[email protected]> @@ -18,25 +18,31 @@ struct { struct jailhouse_system header; __u64 cpus[1]; - struct jailhouse_memory mem_regions[4]; + struct jailhouse_memory mem_regions[14]; struct jailhouse_irqchip irqchips[3]; + struct jailhouse_pci_device pci_devices[2]; } __attribute__((packed)) config = { .header = { .signature = JAILHOUSE_SYSTEM_SIGNATURE, .revision = JAILHOUSE_CONFIG_REVISION, .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE, .hypervisor_memory = { - .phys_start = 0xffc00000, + .phys_start = 0xfdc00000, .size = 0x00400000, }, .debug_console = { .address = 0x30860000, .size = 0x1000, .type = JAILHOUSE_CON_TYPE_IMX, - .flags = JAILHOUSE_CON_ACCESS_MMIO | + .flags = JAILHOUSE_CON_TYPE_IMX | + JAILHOUSE_CON_ACCESS_MMIO | JAILHOUSE_CON_REGDIST_4, }, .platform_info = { + .pci_mmconfig_base = 0xbfb00000, + .pci_mmconfig_end_bus = 0, + .pci_is_virtual = 1, + .arm = { .gic_version = 3, .gicd_base = 0x38800000, @@ -47,9 +53,11 @@ struct { .root_cell = { .name = "imx8mq", + .num_pci_devices = ARRAY_SIZE(config.pci_devices), .cpu_set_size = sizeof(config.cpus), .num_memory_regions = ARRAY_SIZE(config.mem_regions), .num_irqchips = ARRAY_SIZE(config.irqchips), + .vpci_irq_base = 51, /* Not include 32 base */ }, }, @@ -58,6 +66,38 @@ struct { }, .mem_regions = { + /* IVHSMEM shared memory region for 00:00.0 */ { + .phys_start = 0xbfd00000, + .virt_start = 0xbfd00000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ , + }, + { + .phys_start = 0xbfd01000, + .virt_start = 0xbfd01000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE , + }, + { + .phys_start = 0xbfd0a000, + .virt_start = 0xbfd0a000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE , + }, + { + .phys_start = 0xbfd0c000, + .virt_start = 0xbfd0c000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ, + }, + { + .phys_start = 0xbfd0e000, + .virt_start = 0xbfd0e000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ, + }, + /* IVSHMEM shared memory regions for 00:01.0 (networking) */ + JAILHOUSE_SHMEM_NET_REGIONS(0xbfe00000, 0), /* MMIO (permissive) */ { .phys_start = 0x00000000, .virt_start = 0x00000000, @@ -68,14 +108,28 @@ struct { /* RAM */ { .phys_start = 0x40000000, .virt_start = 0x40000000, - .size = 0xbfb00000, + .size = 0x7fb00000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE, }, - /* IVSHMEM shared memory region for 00:00.0 */ { - .phys_start = 0xffb00000, - .virt_start = 0xffb00000, + /* Linux Loader */{ + .phys_start = 0xbff00000, + .virt_start = 0xbff00000, .size = 0x100000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE, + }, + /* Inmate memory */{ + .phys_start = 0xc0000000, + .virt_start = 0xc0000000, + .size = 0x3dc00000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE, + }, + /* OP-TEE reserved memory */{ + .phys_start = 0xfe000000, + .virt_start = 0xfe000000, + .size = 0x2000000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, }, }, @@ -103,4 +157,27 @@ struct { }, }, }, + + .pci_devices = { + { /* IVSHMEM 0000:00:00.0 (demo) */ + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 0, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 0, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + { /* IVSHMEM 0000:00:01.0 (networking) */ + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 0, + .bdf = 1 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 5, + .shmem_dev_id = 0, + .shmem_peers = 2, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH, + }, + }, }; -- 2.17.1 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/20200409140447.4244-1-alice.guo%40nxp.com.
