On Wed, Apr 22, 2020 at 08:42:32AM +0200, Jan Kiszka wrote: > On 27.03.19 13:18, Marco Solieri wrote: > > Predictability of memory access latency is severely menaced by the > > multi-core architectures where the last level of cache (LLC) is > > shared, jeopardizing applicability of many Arm platform in real-time > > critical and mixed-criticality scenarios. Support for cache coloring > > is introduced, a transparent software technique allowing > > partitioning the LLC to avoid mutual interference between inmates. > > [...] > > Thanks for updating this! I will refresh my caches on the topic and > provide feedback soon (I already have some questions and remarks but > I'd like to double-check them).
Looking forward to hear from you. > As you likely read, there are better chances in sight to also address > the root cell issue by booting Jailhouse from a loader. I share the same view. On the other hand, it ties the cache colouring with the Linux-independent boot. This is not ideal from an quality perspective, because it introduces a dependency between otherwise unrelated features, including one definitely optional (as long as Jailhouse will stay a "Linux-based hypervisor"). Also, from a process perspective, it forces the colouring-related activities and deliveries to be postponed after reaching a somewhat stable architecture for the independent loader (colouring pages is a loader matter). The other option is the hot-remapping of the root-cell memory, which we already wrote and tested on an older version of Jailhouse extended with a SMMU support. From a quality perspective, it looks comparable, and it does not introduces constraints on the development process. > That would then leave us only with the question how to handle the > hypervisor itself /wrt coloring. Correct. > Provided that can buy us worthwhile improvements. We already have experimentally proven on two other hypervisors (Xen and Bao) that the interrupt response time hugely depends on the cache performances of the hypervisor's routines for guest injection. Cache partitioning is therefore mandatory for predictability. -- Marco Solieri, Ph.D. Research Fellow High-Performance Real-Time Lab Università degli Studi di Modena e Reggio Emilia Ufficio 1.35 - Edificio Matematica - 213/b, via Campi - 41125 Modena Tel: +39-059-205-55-10 -- OpenPGP: Ox75822E7E -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/20200422072259.sc2au24ksnt6j7jy%40carbon.xt3.it.
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