On 02/07/20 5:14 pm, Jan Kiszka wrote:
On 02.07.20 12:03, Peng Fan wrote:
Hi Jan
https://events19.linuxfoundation.org/wp-content/uploads/2018/07/Consolidate-Real-Time-and-HMI-with-ACRN-Hypervisor.pdf
Have you ever see this? Page 13, there is a compare between ACRN and
jailhouse on X86.
So it show ACRN a bit better? But is there any big differences in
design? I doubt this.
You also need to read the paper where the stats came from: They
implemented APIC (GIC equivalent) pass-through also in ACRN, a feature
that Jailhouse introduced in 2013, and then tried to compare that two
Jailhouse and also RT-KVM. Unfortunately, there were configuration
mistakes in both of those other setup. The one in Jailhouse they found
themselves, redid the measurements, unsurprisingly found both to be the
same then (no hypervisor involved anymore), but they didn't update their
graphs, even not in the paper. The graphs where simply copied into that
presentation.
I attended that session and offered the presenter afterwards to review
their results in the future if those are taken over a stack they are not
familiar with. That would have also helped to avoid the architectural
mistake in their RT-KVM measurement setup which gave them result of by
one order of magnitude.
BTW, regarding direct interrupt delivery on ARM: In
https://lwn.net/Articles/820830, it is reported that Bao has "found a
way to map interrupts directly into guests". I didn't find the time yet
to check if that is actually exit-free delivery, and that as a smart
trick or rather a problematic hack. Or if that sentence is rather a
misunderstanding. There is also the sentence: "Interrupts [...] have to
be mediated through the hypervisor, which is unfortunate since that
increases latency."
I found this interesting and tried to read more about this.
I found some commits at [1] which does the direct injection.
Here is my rough understanding:
* He is not setting the HCR_EL.FMO bit and that way all virtual
interrupts are turned off
* There is a new handler for handling "lower_el_aarch64_fiq"
which ends up being handled by the Hypervisor
* GICD is still being emulated so guests won't be able to route
interrupts to wrong CPUs. Isolation is maintained
* For triggering interrupts from Hypervisor (SGIs, etc) he is using SMC
calls and has a new service implemented in the ATF [2]
* I could not understand how the lower_el_aarch64_fiq exception is fired
so that the Hypervisor is invoked
My guess is that most of the code change ihere s to enable interrupts in
the Hypervisor. Resetting HCR_EL2.FMO would send the interrupts at EL1
directly.
[1]
https://github.com/bao-project/bao-hypervisor/commit/ac41859fc26df8cbb16b25ca949f07f00c1d35a5
[2]
https://github.com/bao-project/bao-hypervisor/commit/0aaa1cade8b5e846503e9b515ae278cfeda30a8b
Nikhil D
Jan
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