From: Peng Fan <[email protected]> Set bit 30 of FPEXC32_EL2 to enables access to the Advanced SIMD and floating-point functionality from all Exception levels.
Set CPACR_EL1.FPEN to not trap accessing to SIMD or floating point registers. Reported-by: Alice Guo <[email protected]> Signed-off-by: Peng Fan <[email protected]> --- hypervisor/arch/arm64/control.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hypervisor/arch/arm64/control.c b/hypervisor/arch/arm64/control.c index 7bc3cab1..a45a5d32 100644 --- a/hypervisor/arch/arm64/control.c +++ b/hypervisor/arch/arm64/control.c @@ -21,6 +21,7 @@ void arm_cpu_reset(unsigned long pc, bool aarch32) { u64 hcr_el2; + u32 fpexc32_el2; /* put the cpu in a reset state */ /* AARCH64_TODO: handle big endian support */ @@ -43,7 +44,7 @@ void arm_cpu_reset(unsigned long pc, bool aarch32) arm_write_sysreg(AFSR1_EL1, 0); arm_write_sysreg(AMAIR_EL1, 0); arm_write_sysreg(CONTEXTIDR_EL1, 0); - arm_write_sysreg(CPACR_EL1, 0); + arm_write_sysreg(CPACR_EL1, 0x300000); arm_write_sysreg(CSSELR_EL1, 0); arm_write_sysreg(ESR_EL1, 0); arm_write_sysreg(FAR_EL1, 0); @@ -57,6 +58,11 @@ void arm_cpu_reset(unsigned long pc, bool aarch32) arm_write_sysreg(TTBR1_EL1, 0); arm_write_sysreg(VBAR_EL1, 0); + arm_read_sysreg(FPEXC32_EL2, fpexc32_el2); + fpexc32_el2 |= (1 << 30); + arm_write_sysreg(FPEXC32_EL2, fpexc32_el2); + arm_read_sysreg(FPEXC32_EL2, fpexc32_el2); + /* wipe timer registers */ arm_write_sysreg(CNTP_CTL_EL0, 0); arm_write_sysreg(CNTP_CVAL_EL0, 0); -- 2.16.4 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/20200820100707.20013-3-peng.fan%40nxp.com.
