Branch: refs/heads/next
Home: https://github.com/siemens/jailhouse
Commit: 5bd098db2e9f591fb5620be4a06b1686e736de50
https://github.com/siemens/jailhouse/commit/5bd098db2e9f591fb5620be4a06b1686e736de50
Author: Peng Fan <[email protected]>
Date: 2020-08-21 (Fri, 21 Aug 2020)
Changed paths:
M hypervisor/arch/arm-common/irqchip.c
Log Message:
-----------
arm: irqchip/gic: Ensure we have an ISB between ack and ->handle_irq
The whole commit message is from Linux Kernel:
commit <39a06b67c2c1>("irqchip/gic: Ensure we have an ISB between ack and
->handle_irq")
Devices that expose their interrupt status registers via system
registers (e.g. Statistical profiling, CPU PMU, DynamIQ PMU, arch timer,
vgic (although unused by Linux), ...) rely on a context synchronising
operation on the CPU to ensure that the updated status register is
visible to the CPU when handling the interrupt. This usually happens as
a result of taking the IRQ exception in the first place, but there are
two race scenarios where this isn't the case.
For example, let's say we have two peripherals (X and Y), where Y uses a
system register for its interrupt status.
Case 1:
1. CPU takes an IRQ exception as a result of X raising an interrupt
2. Y then raises its interrupt line, but the update to its system
register is not yet visible to the CPU
3. The GIC decides to expose Y's interrupt number first in the Ack
register
4. The CPU runs the IRQ handler for Y, but the status register is stale
Case 2:
1. CPU takes an IRQ exception as a result of X raising an interrupt
2. CPU reads the interrupt number for X from the Ack register and runs
its IRQ handler
3. Y raises its interrupt line and the Ack register is updated, but
again, the update to its system register is not yet visible to the
CPU.
4. Since the GIC drivers poll the Ack register, we read Y's interrupt
number and run its handler without a context synchronisation
operation, therefore seeing the stale register value.
In either case, we run the risk of missing an IRQ. This patch solves the
problem by ensuring that we execute an ISB in the GIC drivers prior
to invoking the interrupt handler. This is already the case for GICv3
and EOIMode 1 (the usual case for the host).
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 59c13520ca5e7e235d1dc93674e92b23ec89fb4d
https://github.com/siemens/jailhouse/commit/59c13520ca5e7e235d1dc93674e92b23ec89fb4d
Author: Peng Fan <[email protected]>
Date: 2020-08-21 (Fri, 21 Aug 2020)
Changed paths:
M hypervisor/arch/arm64/Makefile
Log Message:
-----------
arm64: Do not use FPU registers in jailhouse
Some compilers default use hardfloat to generate instructions,
so it will use some FPU/NEON registers to do some optimization.
However some inmates might use FPU/NEON registers do some
calculation such as vector/audio and etc. So we need to disable
jailhouse use these registers. Use `-march=armv8-a+nofp` for this.
Reported-by: Michal Hanak <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: ac290aab988018282f333c6182e271a9fc1e3738
https://github.com/siemens/jailhouse/commit/ac290aab988018282f333c6182e271a9fc1e3738
Author: Peng Fan <[email protected]>
Date: 2020-08-21 (Fri, 21 Aug 2020)
Changed paths:
M hypervisor/arch/arm64/control.c
M hypervisor/arch/arm64/include/asm/sysregs.h
Log Message:
-----------
arm64: allow accessing simd/floating-point registers in inmate
Set bit 30 of FPEXC32_EL2 to enables access to the Advanced SIMD and
floating-point functionality from all Exception levels.
Set CPACR_EL1.FPEN to not trap accessing to SIMD or floating point
registers.
Reported-by: Alice Guo <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
[Jan: replaced CPACR_EL1_FPEN(3) with CPACR_EL1_FPEN_ALL]
Signed-off-by: Jan Kiszka <[email protected]>
Commit: d557c02606ba1f38bb803935da6bffab9cc986ef
https://github.com/siemens/jailhouse/commit/d557c02606ba1f38bb803935da6bffab9cc986ef
Author: Peng Fan <[email protected]>
Date: 2020-08-21 (Fri, 21 Aug 2020)
Changed paths:
M hypervisor/arch/arm/Makefile
Log Message:
-----------
arm: pass -march=armv7ve to KBUILD_AFLAGS
Some toolchains might not have this flag default set, so when compiling,
there will be error that "dsb not supported" in cache.S.
So pass the flag to force toolchain use v7.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 2f0c8774eef8abec46daf7c98ac0057df514c739
https://github.com/siemens/jailhouse/commit/2f0c8774eef8abec46daf7c98ac0057df514c739
Author: Peng Fan <[email protected]>
Date: 2020-08-21 (Fri, 21 Aug 2020)
Changed paths:
M inmates/Makefile
Log Message:
-----------
inmates: Makefile: add -march=armv7ve
Add -march=armv7ve to avoid build error
that ".virt extension not supported".
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Compare:
https://github.com/siemens/jailhouse/compare/ce10986e6637...2f0c8774eef8
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