Branch: refs/heads/coverity_scan
Home: https://github.com/siemens/jailhouse
Commit: a8d033c65dbb8667fc795e16aa4ce60dd45b18f0
https://github.com/siemens/jailhouse/commit/a8d033c65dbb8667fc795e16aa4ce60dd45b18f0
Author: Daniel Sangorrin <[email protected]>
Date: 2020-08-27 (Thu, 27 Aug 2020)
Changed paths:
M Documentation/debug-output.md
Log Message:
-----------
Documentation: fix display resolution number
I was wondering why the configuration size didn't match
the multiplication and then I realised there was an
errata.
Signed-off-by: Daniel Sangorrin <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 7bcab7c38b2c853ec068b35d61205ef660fceaac
https://github.com/siemens/jailhouse/commit/7bcab7c38b2c853ec068b35d61205ef660fceaac
Author: Jakub Luzny <[email protected]>
Date: 2020-08-27 (Thu, 27 Aug 2020)
Changed paths:
M configs/arm64/dts/inmate-rpi4.dts
M configs/arm64/rpi4-inmate-demo.c
M configs/arm64/rpi4-linux-demo.c
M configs/arm64/rpi4.c
Log Message:
-----------
configs: arm64: Add support for RPi4 with more than 1G of memory
Add the required memory regions to support 2G, 4G and 8G RAM variants
of the Raspberry Pi 4. Tested on all the bigger variants, not on 1G, as I don't
have one on hand and it's not available anymore.
Also moved the memory used by Jailhouse for the hypervisor and cells from
0x30000000 to 0x20000000 to avoid conflict with GPU memory. That is fine for
gpu_mem setting of up to 256. The memory is supposed to be reserved using
reserved-memory node in the device tree.
To support variants with >2G RAM, the PCI MMIO config space was moved into the
ARM Local Peripherals address range, into free space behind the GIC.
Signed-off-by: Jakub Luzny <[email protected]>
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 8e1aea00f77d1c1a4b2313255966b741c2f1fd93
https://github.com/siemens/jailhouse/commit/8e1aea00f77d1c1a4b2313255966b741c2f1fd93
Author: Jan Kiszka <[email protected]>
Date: 2020-08-29 (Sat, 29 Aug 2020)
Changed paths:
M hypervisor/arch/arm-common/gic-v2.c
Log Message:
-----------
arm-common: gicv2: Fix byte access to ITARGETR
Byte-size write accesses overwrote all fields the issuing cell owned,
not only the target byte. And byte-size read accesses may have returned
the wrong value. This was broken since the beginning, just wasn't
stressed properly so far. Latest jailhouse-enabling/5.4-rpi revealed it
finally.
Fixes: ee6b35ba9037 ("arm: GICv2: handle SPI routing")
Signed-off-by: Jan Kiszka <[email protected]>
Commit: e2b94aed34874271a9ede06bf4521b4f16ea8b86
https://github.com/siemens/jailhouse/commit/e2b94aed34874271a9ede06bf4521b4f16ea8b86
Author: Jan Kiszka <[email protected]>
Date: 2020-09-05 (Sat, 05 Sep 2020)
Changed paths:
M Kbuild
M configs/Makefile
M hypervisor/Makefile
M hypervisor/arch/arm-common/Kbuild
M hypervisor/arch/arm/Kbuild
M hypervisor/arch/arm64/Kbuild
M hypervisor/arch/x86/Kbuild
M inmates/lib/arm-common/Makefile.lib
M inmates/lib/arm/Makefile
M inmates/lib/arm/Makefile.lib
M inmates/lib/arm64/Makefile
M inmates/lib/arm64/Makefile.lib
M inmates/lib/x86/Makefile
M inmates/lib/x86/Makefile.lib
A scripts/always-compat.mk
M tools/Makefile
Log Message:
-----------
kbuild: Avoid deprecated 'always'
Switch to 'always-y' as suggested by 5.9.
For older kernels, we need to set 'always' to 'always-y'. This has to
happen conditionally in order to avoid warnings from 5.9 onward.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: bf1953f94603d8222e545d531221f93ed640f97e
https://github.com/siemens/jailhouse/commit/bf1953f94603d8222e545d531221f93ed640f97e
Author: Jan Kiszka <[email protected]>
Date: 2020-09-06 (Sun, 06 Sep 2020)
Changed paths:
M driver/main.c
Log Message:
-----------
driver: Adjust to kernel 5.8 and 5.9
Several things changed and require tuning:
- __get_vm_area is gone, switch to __get_vm_area_caller which now
requires another kernel patch to export it (pointless to try
RESOLVE_EXTERNAL_SYMBOL since 5.7)
- cr4_init_shadow was hidden from modules; set/clear VMXE directly
instead so that the shadow is aligned to the real state; no action
needed on AMD as EFER is carrying SVME
- include asm/apic.h explicitly for lapic_timer_period
Signed-off-by: Jan Kiszka <[email protected]>
Commit: e268d2fcf4d0c391ee961703b3f4478c4ebca863
https://github.com/siemens/jailhouse/commit/e268d2fcf4d0c391ee961703b3f4478c4ebca863
Author: Jan Kiszka <[email protected]>
Date: 2020-09-07 (Mon, 07 Sep 2020)
Changed paths:
M pyjailhouse/sysfs_parser.py
Log Message:
-----------
pyjailhouse: sysfs_parser: Fix wording of parse_iomem_tree comment
Makes it easier readable. No functional changes.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 07378a910b85a911caa14eaf7d67d65cfdd6fc51
https://github.com/siemens/jailhouse/commit/07378a910b85a911caa14eaf7d67d65cfdd6fc51
Author: Jan Kiszka <[email protected]>
Date: 2020-09-07 (Mon, 07 Sep 2020)
Changed paths:
M pyjailhouse/sysfs_parser.py
Log Message:
-----------
pyjailhouse: sysfs_parser: Filter out AMD IOMMU memory regions
In case they are enabled while parsing the tree. Analogously to DMAR on
Intel, except that we do not need to keep them.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 2403bc4d3d0aac83ff0732ed24ce4473744f1322
https://github.com/siemens/jailhouse/commit/2403bc4d3d0aac83ff0732ed24ce4473744f1322
Author: Jan Kiszka <[email protected]>
Date: 2020-09-07 (Mon, 07 Sep 2020)
Changed paths:
M pyjailhouse/sysfs_parser.py
Log Message:
-----------
pyjailhouse: sysfs_parser: Return true size from IORegion
Avoid having to override the size method in PortRegion and rather do the
correct calculation in IORegion already. This does not affect the
rounding in MemRegion.size.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 231c39f4b31e25d8ef413533e875ad3193a54e97
https://github.com/siemens/jailhouse/commit/231c39f4b31e25d8ef413533e875ad3193a54e97
Author: Jan Kiszka <[email protected]>
Date: 2020-09-07 (Mon, 07 Sep 2020)
Changed paths:
M pyjailhouse/sysfs_parser.py
Log Message:
-----------
pyjailhouse: sysfs_parser: Always walk reserved regions with children
Newer kernels and/or certain platforms (seen on AMD R1505G) list a all
PCI resources and some ACPI resources behind a top-level reserved
region. Skipping it leaves the config fairly incomplete.
Also fix up a trivial flake8 reporting at this chance.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: c54b26397441ea9e580aba317071f5f98050f194
https://github.com/siemens/jailhouse/commit/c54b26397441ea9e580aba317071f5f98050f194
Author: Jan Kiszka <[email protected]>
Date: 2020-09-07 (Mon, 07 Sep 2020)
Changed paths:
M pyjailhouse/sysfs_parser.py
Log Message:
-----------
pyjailhouse: sysfs_parser: Factor out MemRegion.is_ram
To be reusing for merging RAM regions.
Signed-off-by: Jan Kiszka <[email protected]>
Commit: 3e1ae553f995e2b23867e5f58633beabf0760583
https://github.com/siemens/jailhouse/commit/3e1ae553f995e2b23867e5f58633beabf0760583
Author: Jan Kiszka <[email protected]>
Date: 2020-09-07 (Mon, 07 Sep 2020)
Changed paths:
M pyjailhouse/sysfs_parser.py
Log Message:
-----------
pyjailhouse: sysfs_parser: Merge adjacent RAM regions
The kernel tends to report regions that are not page-aligned but
directly adjacent. Adding them as-is into the config will make accesses
fail because the regions will end up as incompletely configured sub-page
regions. Detect such cases and merge the regions.
Signed-off-by: Jan Kiszka <[email protected]>
Compare:
https://github.com/siemens/jailhouse/compare/6d7eed9ccf14...3e1ae553f995
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