From: Jan Kiszka <[email protected]> This was simply wrong: We must use the same settings for the SMMU as for the MMU because we share the page tables. We can pick up VTCR_CELL for this, just like SMMUv3 does, we just need to mask out reserved bits.
Signed-off-by: Jan Kiszka <[email protected]> --- hypervisor/arch/arm64/smmu.c | 63 ++---------------------------------- 1 file changed, 3 insertions(+), 60 deletions(-) diff --git a/hypervisor/arch/arm64/smmu.c b/hypervisor/arch/arm64/smmu.c index 66453b67..ca86eed5 100644 --- a/hypervisor/arch/arm64/smmu.c +++ b/hypervisor/arch/arm64/smmu.c @@ -23,27 +23,6 @@ #define ARM_SMMU_FEAT_VMID16 (1 << 6) #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) -#define ARM_64_LPAE_S2_TCR_RES1 (1 << 31) -#define ARM_LPAE_TCR_TG0_4K (0 << 14) -#define ARM_LPAE_TCR_TG0_64K (1 << 14) -#define ARM_LPAE_TCR_SH0_SHIFT 12 -#define ARM_LPAE_TCR_SH_IS 3 -#define ARM_LPAE_TCR_ORGN0_SHIFT 10 -#define ARM_LPAE_TCR_IRGN0_SHIFT 8 -#define ARM_LPAE_TCR_RGN_WBWA 1 -#define ARM_LPAE_TCR_RGN_WB 3 -#define ARM_LPAE_TCR_SL0_SHIFT 6 -#define ARM_LPAE_TCR_SL0_LVL_1 1 -#define ARM_LPAE_TCR_T0SZ_SHIFT 0 -#define ARM_LPAE_TCR_PS_SHIFT 16 -#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL -#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL -#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL -#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL -#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL -#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL -#define ARM_LPAE_TCR_PS_52_BIT 0x6ULL - #define TLB_LOOP_TIMEOUT 1000000 /* SMMU global address space */ @@ -162,6 +141,8 @@ #define SCTLR_TRE (1 << 1) #define SCTLR_M (1 << 0) +#define TCR_RES0 (BIT_MASK(31, 23) | BIT_MASK(20, 19)) + #define FSR_MULTI (1 << 31) #define FSR_SS (1 << 30) #define FSR_UUT (1 << 8) @@ -280,48 +261,10 @@ static int arm_smmu_init_context_bank(struct arm_smmu_device *smmu, struct arm_smmu_cb *cb = &smmu->cbs[cfg->id]; struct paging_structures *pg_structs; unsigned long cell_table; - u32 reg; cb->cfg = cfg; - /* VTCR */ - reg = ARM_64_LPAE_S2_TCR_RES1 | - (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) | - (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) | - (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT); - - reg |= (ARM_LPAE_TCR_SL0_LVL_1 << ARM_LPAE_TCR_SL0_SHIFT); - reg |= ARM_LPAE_TCR_TG0_4K; - - switch (smmu->pa_size) { - case 32: - reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_PS_SHIFT); - break; - case 36: - reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_PS_SHIFT); - break; - case 40: - reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_PS_SHIFT); - break; - case 42: - reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_PS_SHIFT); - break; - case 44: - reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_PS_SHIFT); - break; - case 48: - reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_PS_SHIFT); - break; - case 52: - reg |= (ARM_LPAE_TCR_PS_52_BIT << ARM_LPAE_TCR_PS_SHIFT); - break; - default: - return trace_error(-EIO); - } - - reg |= (64ULL - smmu->ipa_size) << ARM_LPAE_TCR_T0SZ_SHIFT; - - cb->tcr[0] = reg; + cb->tcr[0] = VTCR_CELL & ~TCR_RES0; pg_structs = &cell->arch.mm; cell_table = paging_hvirt2phys(pg_structs->root_table); -- 2.26.2 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/7ee8dd23048980b9e747693e5c72fc158c8abb01.1601838005.git.jan.kiszka%40siemens.com.
